Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A semiconductor device includes a first concentric structure extending along a vertical direction and wrapping around a first conductor structure. The semiconductor device includes a second concentric structure extending along the vertical direction and wrapping around a second conductor structure. The semiconductor device includes a third conductor structure extending along the vertical direction, wherein the third conductor structure is interposed between and spaced from the first and second concentric structures along a first lateral direction. The semiconductor device includes a fourth conductor structure extending along the first lateral direction. The fourth conductor structure at least partially wraps around each of the first concentric structure, the third conductor structure, and the second concentric structure.

Abstract: The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.

Abstract: A method for manufacturing a semiconductor device includes forming a first memory cell, which includes forming a first conductor structure extending along a lateral direction; forming a first memory film comprising a first portion wrapping around a first portion of the first conductor structure; forming a first semiconductor film wrapping around the first portion of the first memory film; forming a second conductor structure that extends along a vertical direction; coupling the second conductor structure to a first end portion of the first semiconductor film along the lateral direction; forming a third conductor structure extends along the vertical direction; and coupling the third conductor structure to a second end portion of the first semiconductor film along the lateral direction. The first conductor structure has a void.

Abstract: A memory device includes a first memory block. The first memory block includes a first memory sub-array and a first interface portion disposed next to the first memory sub-array. The first interface portion has a plurality of first control structures formed as a first staircase profile. The first memory block further includes a plurality of first interconnect structures landing on a corresponding one of the plurality of first control structures, and a plurality of second interconnect structures configured to electrically couple a corresponding one of the plurality of first interconnect structures to a first transistor. The memory device further includes a first test structure and a second test structure disposed next to the first memory block, each configured to simulate electrical connections of the plurality of second interconnect structures. The first and second test structures are electrically coupled to each other and are electrically isolated form the first memory block.

Abstract: Memory devices and a method of fabricating memory devices are disclosed. In one aspect, the method includes forming a plurality of first transistors in a first area and a plurality of second transistors in a second area and forming a stack over the second area. The method includes forming a memory array portion and an interface portion through the stack. The memory array portion includes memory strings and the interface portion includes first conductive structures extending along a lateral direction. The method further includes simultaneously forming second conductive structures in the first area and forming third conductive structures in the second area. The second conductive structures each vertically extend to electrically couple to at least one of the first transistors, and the third conductive structures each vertically extend through one of the memory strings to electrically couple to at least one of the second transistors.

Abstract: A semiconductor device includes a memory array that includes a plurality of memory strings each extending in a vertical direction and having a plurality of memory cells. Each of the plurality of memory cells has a drain terminal and a source terminal, and the drain terminal of a first one of the plurality of memory cells and the source terminal of a second one of the plurality of memory cells are electrically coupled to a first conductor structure and a second conductor structure respectively extending in a lateral direction. Each of the plurality of memory strings further includes a vertical memory layer, and a semiconductor channel having a vertical portion coupled to the memory layer and a lateral portion coupled to a top surface of the first conductor structure. The top surface of the first conductor structure is not in contact with the memory layer.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: A method for fabricating memory devices includes forming a first portion of a memory device that includes a first device portion and one or more first interface portions. The first device portion includes a plurality of first memory strings, each of which includes a plurality of first memory cells vertically separated from one another. Each of the one or more first interface portions, laterally abutted to one side of the first device portion, includes a plurality of first word lines (WLs). The method further includes forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) in the first device portion. The method further includes forming a first seal ring structure that laterally encloses both the first device portion and the first interface portion concurrently with forming the pluralities of SLs and BLs.

Abstract: A method for manufacturing a semiconductor device includes forming a first CPODE dummy poly gate and a second CPODE dummy poly gate on a semiconductor substrate; removing the first CPODE dummy poly gate and a portion of the semiconductor substrate therebelow to form a first trench extending into the semiconductor substrate; filling the first trench with a first dielectric material to form a first isolation structure to isolate the first and second transistors from each other; removing the second CPODE dummy poly gate and a portion of the semiconductor substrate therebelow to form a second trench extending into the semiconductor substrate; and filling the second trench with a second dielectric material having a dielectric composition different from that of the first dielectric material to form a second isolation structure to isolated the third and fourth transistors from each other.

Abstract: A semiconductor device comprises a source and a pair of drains disposed on either side of the source in a first direction and spaced apart therefrom. A channel layer extending in the first direction is disposed on at least one radially outer surface of the source and the pair of drains in a second direction perpendicular to the first direction. A memory layer extending in the first direction is disposed on a radially outer surface of the channel layer in the second direction. At least one gate layer that extends in the first direction, is disposed on a radially outer surface of the memory layer in the second direction. A gate extension structure extends from the each of the drains at least part way towards the source in the first direction, and is located proximate to, and in contact with each of the channel layer and the corresponding drain.

Abstract: A memory device comprises a word line, a gate dielectric layer, a semiconductor layer, a source line, and a resistance-switchable element. The word line is over a substrate. The gate dielectric layer is on a sidewall of the word line. The semiconductor layer is on a sidewall of the gate dielectric layer. The source line is in contact with a first region of a sidewall of the semiconductor layer. The resistance-switchable element is in contact with a second region of the sidewall of the semiconductor layer.

Abstract: A semiconductor die comprises: a device portion comprising an array of semiconductor devices extending in a first direction; and at least one interface portion located adjacent to an axial end of the device portion in the first direction. The at least one interface portion has a staircase profile in a vertical direction. The interface portion comprises: a stack comprising a plurality of gate layers and a plurality of insulating layers alternatively stacked on top of one another, and memory layers interposed between each of the plurality of gate layers and the plurality of insulating layers.

Abstract: A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and channel layers. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure.

Abstract: A semiconductor device includes a first concentric structure extending along a vertical direction and wrapping around a first conductor structure. The semiconductor device includes a second concentric structure extending along the vertical direction and wrapping around a second conductor structure. The semiconductor device includes a third conductor structure extending along the vertical direction, wherein the third conductor structure is interposed between and spaced from the first and second concentric structures along a first lateral direction. The semiconductor device includes a fourth conductor structure extending along the first lateral direction. The fourth conductor structure at least partially wraps around each of the first concentric structure, the third conductor structure, and the second concentric structure.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The method includes forming an isolation structure in a substrate to define an isolating region and forming a capacitor structure on an upper surface of the isolation structure and comprising a first semiconductor structure and a second semiconductor structure separated by an insulator pattern. The first semiconductor structure and the second semiconductor structure are formed with upper surfaces aligned with one another.

Abstract: A device includes stacking structures, first conductive contacts, first drivers and second conductive contacts. Each of the stacking structures includes alternately stacked first conductive lines and first dielectric layers, and the stacking structures are shaped into first staircase structures and second staircase structures at first and second sides, respectively. The first conductive contacts are bonded to the first conductive lines respectively. The second conductive contacts are bonded to the first drivers respectively, wherein the first conductive contacts and the second conductive contacts are bonded and disposed between the first conductive lines and the first drivers.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A semiconductor device, comprises a source, and a drain spaced apart from the source in a first direction. A channel layer is disposed on radially outer surfaces of the source and the drain in a second direction orthogonal to the first direction. A memory layer is disposed on a radially outer surface of the channel layer. A via is disposed at an axial end of the drain and is configured to electrically couple the drain to a global drain line. The via comprises a via base extending in a plane defined by the first direction and a second direction perpendicular to the first direction, and structured to contact the corresponding global drain line, and via sidewalls extending from outer peripheral edges of the base towards the drain. The via defines an internal cavity within which at least a portion of the axial end of the drain is disposed.