Abstract: Provided is an anti-Henipavirus monoclonal antibody having broad spectrum neutralization activity, wherein the antibody comprises a macaque variable region and a human constant region. The antibody of the present invention has good binding activity to both Nipah virus glycoprotein G and Hendra virus glycoprotein G, can effectively neutralize Nipahpseudovirus and Hendra pseudovirus, and can be used for preparing drugs for treating Henipavirus diseases.

Abstract: Disclosed is a monoclonal antibody against the Rift Valley fever virus. The antibody is screened and obtained by means of flow cytometric sorting and single-cell PCR technology, and has a unique CDR region. Further disclosed is the use of the antibody in the preparation of a drug for treating Rift Valley fever. The monoclonal antibody against the Rift Valley fever virus has high efficiency and specific activity against the Rift Valley fever virus; and also has the characteristics of high expression, high degree of humanization and good stability, and is suitable for industrial production.

Abstract: Provided is an anti-Henipavirus monoclonal antibody having broad spectrum neutralization activity, wherein the antibody comprises a macaque variable region and a human constant region. The antibody of the present invention has good binding activity to both Nipah virus glycoprotein G and Hendra virus glycoprotein G, can effectively neutralize Nipahpseudovirus and Hendra pseudovirus, and can be used for preparing drugs for treating Henipavirus diseases.

Abstract: Disclosed in the present invention is an anti-Nipah virus monoclonal antibody having neutralization activity. The antibody consists of a monkey-derived variable region and a human constant region, and both light and heavy chains of the monkey-derived variable region have unique CDR regions. The antibody provided by the present invention has an excellent antigen binding capability, and has good binding activity with Bangladesh Nipah virus and Malaysia Nipah virus glycoprotein G. The antibody can effectively neutralize the Nipahpseudovirus. Moreover, the neutralization activity of the antibody is enhanced as the concentration of the antibody increases, and nearly 100% neutralization of the Nipahpseudovirus can be achieved at a concentration of 1 ?g/mL. Also disclosed in the present invention is an application of the monoclonal antibody against the Nipah virus glycoprotein G in preparation of a Nipah virus treatment drug.

Abstract: Disclosed is a privacy-preserving neural network prediction system in the technical field of information security. The system includes a client, a server and a third party device. Off-line, the client, the server and the third party complete model parameter sharing through negotiation. Online, the client sends/shares input data to the server. The client and the server use a secure calculating protocol to jointly execute neural network prediction with privacy preservation. The server returns an obtained prediction result to the client, and the client reconstructs the prediction result. Only one round of communication interaction is required, and the amount of communication overhead is reduced, so that the communication efficiency significantly improves. The calculations in the present system may be based on a ring, rather than a domain. The present system also (re)customizes the offline protocol, which improves the offline efficiency and requires only a lightweight secret sharing operation.

Abstract: Consistent with an example embodiment, there is a power regulator arrangement with variable current capacity providing power from a power supply to a load having variable demand. As a load, a high-performance microprocessor has several modes of operation. At the highest speed setting, it demands a lot of current. At slower clock speeds and during state retention, the processor has a very low current consumption. Using a single regulator, the current efficiency may be very low during long standby periods. To increase the efficiency even at lower load currents, a scheme is based on parallel operation of multiple regulators having different load ranges, for example, a “low, “medium,” and “high” range regulators. Having knowledge of the load current profile, the regulators can be adjusted such that the peak of the efficiency curve matches the load profile of the regulator. The efficiency of the power regulator arrangement is enhanced throughout the range of power demanded by the load.

Abstract: Consistent with an example embodiment, there is a power regulator arrangement with variable current capacity providing power from a power supply to a load having variable demand. As a load, a high-performance microprocessor has several modes of operation. At the highest speed setting, it demands a lot of current. At slower clock speeds and during state retention, the processor has a very low current consumption. Using a single regulator, the current efficiency may be very low during long standby periods. To increase the efficiency even at lower load currents, a scheme is based on parallel operation of multiple regulators having different load ranges, for example, a “low, “medium,” and “high” range regulators. Having knowledge of the load current profile, the regulators can be adjusted such that the peak of the efficiency curve matches the load profile of the regulator. The efficiency of the power regulator arrangement is enhanced throughout the range of power demanded by the load.

Abstract: A controller receives an M-bit input and generates, in response, an S-bit upper range binary data feeding S-bit high range DAC and an R-bit lower range data feeding an R-bit low range DAC. The controller detects transition points in the M-bit input and in response, adds a transition data to the S-bit data equal to at least one least significant bit of the S-bit data and subtracts a value from the R-bit data equal to the transition data. The transition points and the transition data are detected and added at points avoiding such transitions at a full scale value of the R-bit data.

Abstract: A controller receives an M-bit input and generates, in response, an S-bit upper range binary data feeding S-bit high range DAC and an R-bit lower range data feeding an R-bit low range DAC. The controller detects transition points in the M-bit input and in response, adds a transition data to the S-bit data equal to at least one least significant bit of the S-bit data and subtracts a value from the R-bit data equal to the transition data. The transition points and the transition data are detected and added at points avoiding such transitions at a full scale value of the R-bit data.