Abstract: A display structure includes a main body, a plurality of light-emitting diode units, and a plurality of light blocking walls. The main body includes a substrate, and a circuit unit disposed on the substrate. The light-emitting diode units are electrically connected to the circuit unit and illuminate outwardly. Each of the light blocking walls is disposed between two adjacent ones of the light-emitting diode units to prevent light interference between the two adjacent ones of the light-emitting diode units.

Abstract: The present invention provides method for operating a multipoint control system, which includes a plurality of controlled units serially connected and each controlled unit has a execution unit and an interpretive unit having a data processing unit and a memory unit, utilizes start packets pass through every one of controlled units which could be modified and transmitted to the next stage to achieve addressing for all of the system. Specifically, an information stream including a first start packet including a first leading message and a plurality of first data packets are transmitted by a controller, and a first address in the first start packet is modified by data processing unit and transmitted to the next stage. In addition, a first data packet corresponding to the first address is retrieved by the interpretive unit and the execution unit is enabled by the interpretive unit.

Abstract: A signal encoder and a signal decoder involves the signal encoder for receiving a data signal and a clock signal, including a first code output terminal and a second code output terminal. When the data signal is logic one, the signal encoder outputs a modulated signal through the first code output terminal, and outputs a fixed level signal through the second code output terminal. When the data signal is logic zero, the signal encoder outputs the fixed level signal through the first code output terminal, and outputs the modulated signal through the second code output terminal. The signal decoder converts the modulated signal and the fixed level signal output from the signal encoder into the data signal and the clock signal.

Abstract: A signal encoder and a signal decoder involves the signal encoder for receiving a data signal and a clock signal, including a first code output terminal and a second code output terminal. When the data signal is logic one, the signal encoder outputs a modulated signal through the first code output terminal, and outputs a fixed level signal through the second code output terminal. When the data signal is logic zero, the signal encoder outputs the fixed level signal through the first code output terminal, and outputs the modulated signal through the second code output terminal. The signal decoder converts the modulated signal and the fixed level signal output from the signal encoder into the data signal and the clock signal.

Abstract: The present invention provides method for operating a multipoint control system. It utilizes start packets pass through every one of controlled units which could be modified and transmitted to the next stage to achieve addressing for all of the system.

Abstract: A video format bridge employs a plurality of techniques to insure that the line buffer does not suffer underflow or overflow conditions, and that the output frame rate matches the input frame rate. The bridge handles the problem of residue lines, addresses fluctuations in the input and output clock rates, and allows adjustment of the ratio of the input and output the number of lines per frame or number of pixels per line so that output device specifications are not exceeded. A single integrated circuit may provided which is adapted to perform a plurality of techniques, and includes resources by which the user is able to enable and disable such techniques as needed for the particular bridging operation being executed.

Abstract: A video format bridge employs a plurality of techniques to insure that the line buffer does not suffer underflow or overflow conditions, and that the output frame rate matches the input frame rate. The bridge handles the problem of residue lines, addresses fluctuations in the input and output clock rates, and allows adjustment of the ratio of the input and output the number of lines per frame or number of pixels per line so that output device specifications are not exceeded. A single integrated circuit may provided which is adapted to perform a plurality of techniques, and includes resources by which the user is able to enable and disable such techniques as needed for the particular bridging operation being executed.