Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a gate spacer formed adjacent to the gate structure, and an etching stop layer adjacent to the gate spacer. The semiconductor structure also includes a gate mask layer formed over the gate structure, and a topmost surface of the gate mask layer is higher than a top surface of the etching stop layer.

Abstract: A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a front-side interconnection structure, and a backside via. The gate structure is across the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the gate structure and are connected to the channel layer. The front-side interconnection structure is on a front-side of the first source/drain epitaxial structure. The backside via is connected to a backside of the first source/drain epitaxial structure. A backside surface of the first source/drain epitaxial structure is at a height between a height of a backside surface of the backside via and a height of a backside surface of the gate structure.

Abstract: A method includes providing a structure having gate structures, source/drain electrodes, a first etch stop layer (ESL), a first interlayer dielectric (ILD) layer, a second ESL, and a second ILD layer. The method includes forming a first etch mask; performing a first etching to the second ILD layer, the second ESL, and the first ILD layer through the first etch mask to form first trenches; depositing a third dielectric layer into the first trenches; forming a second etch mask; and performing a second etching to the second ILD layer, the second ESL, the first ILD layer, and the first ESL through the second etch mask, thereby forming second trenches, wherein the second trenches expose some of the source/drain electrodes, and the third dielectric layer resists the second etching. The method further includes depositing a metal layer into the second trenches.

Abstract: A method includes providing a structure having source/drain electrodes and a first dielectric layer over the source/drain electrodes; forming a first etch mask covering a first area of the first dielectric layer; performing a first etching process to the first dielectric layer, resulting in first trenches over the source/drain electrodes; filling the first trenches with a second dielectric layer that has a different material than the first dielectric layer; removing the first etch mask; performing a second etching process including isotropic etching to the first area of the first dielectric layer, resulting in a second trench above a first one of the source/drain electrodes; depositing a metal layer into at least the second trench; and performing a chemical mechanical planarization (CMP) process to the metal layer.

Abstract: A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a dummy fin structure, a mask layer, a first source/drain contact, and an isolation plug. The gate structure crosses the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer. The dummy fin structure is in contact with the first source/drain epitaxial structure. The mask layer is over the dummy fin structure. The first source/drain contact is over and electrically connected to the first source/drain epitaxial structure. The isolation plug is over the mask layer and in contact with the first source/drain contact. The isolation plug is directly over the first source/drain contact and the mask layer.

Abstract: A method includes providing a structure having source/drain electrodes and a first dielectric layer over the source/drain electrodes; forming a first etch mask covering a first area of the first dielectric layer; performing a first etching process to the first dielectric layer, resulting in first trenches over the source/drain electrodes; filling the first trenches with a second dielectric layer that has a different material than the first dielectric layer; removing the first etch mask; performing a second etching process including isotropic etching to the first area of the first dielectric layer, resulting in a second trench above a first one of the source/drain electrodes; depositing a metal layer into at least the second trench; and performing a chemical mechanical planarization (CMP) process to the metal layer.

Abstract: A method for manufacturing a semiconductor device includes: forming a feature in a dielectric layer disposed on a semiconductor substrate, the dielectric layer including silicon oxide, the feature extending downwardly from a top surface of the dielectric layer and including silicon, a nitride compound, a low-k dielectric material other than silicon oxide, or combinations thereof; and selectively etching the dielectric layer using an etchant composition to form a trench extending downwardly from the top surface of the dielectric layer, the etchant composition including a hydrogen halide and a nitrogen-containing compound represented by Formula (A), wherein R1, R2, R3 are each independently hydrogen, methyl, or ethyl.

Abstract: A device includes a substrate. A channel region of a transistor overlies the substrate and a source/drain region is in contact with the channel region. The source/drain region is adjacent to the channel region along a first direction. A source/drain contact is disposed on the source/drain region. A gate electrode is disposed on the channel region and a gate contact is disposed on the gate electrode. A first low-k dielectric layer is disposed between the gate contact and the source/drain contact along the first direction.

Abstract: A device includes a substrate and a gate structure wrapping around at least one vertical stack of nanostructure channels. The device includes a source/drain region abutting the gate structure, and a source/drain contact over the source/drain region. The device includes an etch stop layer laterally between the source/drain contact and the gate structure and having a first sidewall in contact with the source/drain contact, and a second sidewall opposite the first sidewall. The device includes a source/drain contact isolation structure embedded in the source/drain contact and having a third sidewall substantially coplanar with the second sidewall of the etch stop layer.

Abstract: A method includes providing a structure having source/drain electrodes and a first dielectric layer over the source/drain electrodes; forming a first etch mask covering a first area of the first dielectric layer; performing a first etching process to the first dielectric layer, resulting in first trenches over the source/drain electrodes; filling the first trenches with a second dielectric layer that has a different material than the first dielectric layer; removing the first etch mask; performing a second etching process including isotropic etching to the first area of the first dielectric layer, resulting in a second trench above a first one of the source/drain electrodes; depositing a metal layer into at least the second trench; and performing a chemical mechanical planarization (CMP) process to the metal layer.