Abstract: A stylus includes a conductive rod, a circuit board, and an antenna. The conductive rod has a first opening. The circuit board is disposed in the conductive rod and includes a ground portion, wherein the conductive rod is electrically connected to the ground portion. The antenna includes a radiating portion and a feeding portion. The feeding portion is electrically connected to the circuit board and extends to the outside of the conductive rod via the first opening. The radiating portion is disposed at the outside of the conductive rod and is electrically connected to the feeding portion.

Abstract: The antenna matching circuit control device with an antenna body includes a sensing module, a processing module, a power adjusting module and a frequency adjusting module. The sensing module senses an object that approaches the antenna body and outputs a sensing signal accordingly. The processing module is coupled to the sensing module and outputs a first control signal and a second control signal according to the sensing signal. The power adjusting module is coupled to the processing module and controls a power amplifier to couple with one of a plurality of first matching circuits according to the first control signal. The frequency adjusting module is coupled to the antenna body and the power adjusting module. The frequency adjusting module controls one of a plurality of second matching circuits to couple with one of the first matching circuits according to the second control signal.

Abstract: The antenna matching circuit control device with an antenna body includes a sensing module, a processing module, a power adjusting module and a frequency adjusting module. The sensing module senses an object that approaches the antenna body and outputs a sensing signal accordingly. The processing module is coupled to the sensing module and outputs a first control signal and a second control signal according to the sensing signal. The power adjusting module is coupled to the processing module and controls a power amplifier to couple with one of a plurality of first matching circuits according to the first control signal. The frequency adjusting module is coupled to the antenna body and the power adjusting module. The frequency adjusting module controls one of a plurality of second matching circuits to couple with one of the first matching circuits according to the second control signal.

Abstract: The antenna matching circuit control device with an antenna body includes a sensing module, a processing module, a power adjusting module and a frequency adjusting module. The sensing module senses an object that approaches the antenna body and outputs a sensing signal accordingly. The processing module is coupled to the sensing module and outputs a first control signal and a second control signal according to the sensing signal. The power adjusting module is coupled to the processing module and controls a power amplifier to couple with one of a plurality of first matching circuits according to the first control signal. The frequency adjusting module is coupled to the antenna body and the power adjusting module. The frequency adjusting module controls one of a plurality of second matching circuits to couple with one of the first matching circuits according to the second control signal.

Abstract: The present invention discloses a system for generating a software TLM model, comprising a processing unit; a compiler coupled to the processing unit to generate target binary codes of a target software; a decompiler coupled to the processing unit to decompile the target binary codes into high level codes, for example C or C++ codes, to generate a functional model of the target software, wherein the functional model includes a plurality of basic blocks; an execution time calculating module coupled to the processing unit to calculate overall execution time of the plurality of the basic blocks of the functional model; a sync point identifying module coupled to the processing unit to identify sync points of the software transaction-level modeling model; and a time annotating module coupled to the processing unit to annotate the overall execution time of the basic blocks and the sync points into the functional model to obtain the software transaction-level modeling model.

Abstract: A stylus includes a conductive rod, a circuit board, and an antenna. The conductive rod has a first opening. The circuit board is disposed in the conductive rod and includes a ground portion, wherein the conductive rod is electrically connected to the ground portion. The antenna includes a radiating portion and a feeding portion. The feeding portion is electrically connected to the circuit board and extends to the outside of the conductive rod via the first opening. The radiating portion is disposed at the outside of the conductive rod and is electrically connected to the feeding portion.

Abstract: A deadlock free synchronization synthesizer for must-happen-before relations in at least two parallel programs or at least two threads each having multiple code segments has an input device to specify a synchronization point to involving code segments for each parallel program or thread and must-happen-before relations to the synchronization point, an analyzing module connected to the input device to detect existence of a deadlock in the parallel programs by using the must-happen-before relations, and a synthesizing module connected to the analyzing module to synthesize a practice code corresponding to the parallel programs if the deadlock existence detection is negative.

Abstract: The present invention discloses a high-parallelism synchronization method for multi-core instruction-set simulation. The proposed method utilizes a new distributed scheduling mechanism for a parallel compiled MCISS. The proposed method can enhance the parallelism of the MCISS so that the computing power of a multi-core host machine can be effectively utilized. The distributed scheduling with the present invention's prediction method significantly shortens the waiting time which an ISS spends on synchronization.

Abstract: The present invention discloses a method for multi-core instruction-set simulation. The proposed method identifies the shared data segment and the dependency relationship between the different cores and thus effectively reduces the number of sync points and lowers the synchronization overhead, allowing multi-core instruction-set simulation to be performed more rapidly while ensuring that the simulation results are accurate. In addition, the present invention also discloses a device for multi-core instruction-set simulation.

Abstract: The present invention discloses a shared-variable-based (SVB) approach for fast and accurate multi-core cache coherence simulation. While the intuitive, conventional approach, synchronizing at either every cycle or memory access, gives accurate simulation results, it has poor performance due to huge simulation overloads. In the present invention, timing synchronization is only needed before shared variable accesses in order to maintain accuracy while improving the efficiency in the proposed shared-variable-based approach.

Abstract: In the present disclosure, the DOM approach for the simulation of OS preemptive scheduling has presented and demonstrated. By maintaining the data-dependency between the software tasks, and guaranteeing the order of shared variable accesses, it can accurately simulate the preemption effect. Moreover, the proposed DOM OS model is implemented to enable preemptive scheduling in SystemC.

Abstract: The present invention discloses a high-parallelism synchronization method for multi-core instruction-set simulation. The proposed method utilizes a new distributed scheduling mechanism for a parallel compiled MCISS. The proposed method can enhance the parallelism of the MCISS so that the computing power of a multi-core host machine can be effectively utilized.

Abstract: The present invention discloses a cycle-count-accurate (CCA) processor modeling, which can achieve high simulation speeds while maintaining timing accuracy of the system simulation. The CCA processor modeling includes a pipeline subsystem model and a cache subsystem model with accurate cycle with accurate cycle count information and guarantees accurate timing and functional behaviors on processor interface. The CCA processor modeling further includes a branch predictor and a bus interface (BIF) to predict the branch of pipeline execution behavior (PEB) and to simulate the data accesses between the processor and the external components via an external bus, respectively. The experimental results show that the CCA processor modeling performs 50 times faster than the corresponding Cycle-accurate (CA) model while providing the same cycle count information as the target RTL model.

Abstract: The antenna matching circuit control device with an antenna body includes a sensing module, a processing module, a power adjusting module and a frequency adjusting module. The sensing module senses an object that approaches the antenna body and outputs a sensing signal accordingly. The processing module is coupled to the sensing module and outputs a first control signal and a second control signal according to the sensing signal. The power adjusting module is coupled to the processing module and controls a power amplifier to couple with one of a plurality of first matching circuits according to the first control signal. The frequency adjusting module is coupled to the antenna body and the power adjusting module. The frequency adjusting module controls one of a plurality of second matching circuits to couple with one of the first matching circuits according to the second control signal.

Abstract: The present invention provides a method for simulating processor power consumption, the method comprises: simulating a simulated processor; utilizing a power analysis model to analyze the simulated processor's execution of at least one fragment of a program, for generating power analysis of a plurality of basic blocks of the at least one fragment; computing at least one power correction factor between the plurality of basic block; utilizing a processing apparatus to generate a simulation model with power annotation based on the power analysis and the at least one power correction factor; and predicting power consumption of the simulated processor based on the simulation model with power annotation.

Abstract: The present invention discloses a system for generating a software TLM model, comprising a processing unit; a compiler coupled to the processing unit to generate target binary codes of a target software; a decompiler coupled to the processing unit to decompile the target binary codes into high level codes, for example C or C++ codes, to generate a functional model of the target software, wherein the functional model includes a plurality of basic blocks; an execution time calculating module coupled to the processing unit to calculate overall execution time of the plurality of the basic blocks of the functional model; a sync point identifying module coupled to the processing unit to identify sync points of the software transaction-level modeling model; and a time annotating module coupled to the processing unit to annotate the overall execution time of the basic blocks and the sync points into the functional model to obtain the software transaction-level modeling model.

Abstract: The present invention discloses a method for multi-core instruction-set simulation. The proposed method identifies the shared data segment and the dependency relationship between the different cores and thus effectively reduces the number of sync points and lowers the synchronization overhead, allowing multi-core instruction-set simulation to be performed more rapidly while ensuring that the simulation results are accurate. In addition, the present invention also discloses a device for multi-core instruction-set simulation.