Patents by Inventor Meng-Hui Lin
Meng-Hui Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11357234Abstract: A food safety quality and performance monitoring system is provided, which is part of Industry 4.0 factory monitoring, including: a slaughter production line monitoring module recording a first monitoring information including quantity, voltage, temperature and humidity, time, and the like; a processing line monitoring module recording a second monitoring information including quantity, temperature and humidity, time, metal detection, and the like; an intelligent central monitoring server storing the first monitoring information and the second monitoring information and allowing a user to register and log in; and a human-machine interface facilitating the security and performance monitoring of the food production line. A food safety quality and performance monitoring method is further provided.Type: GrantFiled: February 22, 2019Date of Patent: June 14, 2022Assignee: Yuan Jin Chuang Enterprise Co., LtdInventors: Hung-Yuan Wu, Meng-Hui Lin
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Patent number: 11052058Abstract: A use of a poultry crude protein extract for preparing an anti-fatigue composition is provided. The poultry crude protein extract is obtained by extraction of poultry meat at high temperature and high pressure and the removal of fat by oil and water separation, and the poultry crude protein extract includes at least branched-chain amino acid (BCAA), histidine, threonine, lysine, and phenylalanine, wherein anti-fatigue entails increasing muscle glycogen concentration, helping to increase exercise tolerance, helping to increase blood urea nitrogen metabolism, and helping to inhibit lactic acid production.Type: GrantFiled: January 21, 2019Date of Patent: July 6, 2021Assignee: Yuan Jin Chuang Enterprise Co., LtdInventors: Hung-Yuan Wu, Meng-Hui Lin
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Publication number: 20200170264Abstract: A food safety quality and performance monitoring system is provided, which is part of Industry 4.0 factory monitoring, including: a slaughter production line monitoring module recording a first monitoring information including quantity, voltage, temperature and humidity, time, and the like; a processing line monitoring module recording a second monitoring information including quantity, temperature and humidity, time, metal detection, and the like; an intelligent central monitoring server storing the first monitoring information and the second monitoring information and allowing a user to register and log in; and a human-machine interface facilitating the security and performance monitoring of the food production line. A food safety quality and performance monitoring method is further provided.Type: ApplicationFiled: February 22, 2019Publication date: June 4, 2020Applicant: Yuan Jin Chuang Enterprise Co.,LtdInventors: Hung-Yuan Wu, Meng-Hui Lin
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Publication number: 20200137987Abstract: The invention relates to an airtight poultry house and an intelligent monitoring automatic control system thereof that collects large data related to growth factor correlation. The intelligent monitoring automatic control system includes: at least one detection module disposed in a processing unit for generating a farming area data according to the airtight state of at least one poultry farming area; at least one control module disposed in the processing unit, wherein each of the at least one control module is provided with a processing unit automatic control rule, and each of the at least one control module is used to automatically control the desired airtight state for the farming environment according to the processing unit automatic control rule and the farming area data and to put the at least one poultry farming area in a negative pressure state; and a database storing the farming area data.Type: ApplicationFiled: March 8, 2019Publication date: May 7, 2020Applicant: Yuan Jin Chuang Enterprise Co.,LtdInventors: Hung-Yuan Wu, Meng-Hui Lin
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Publication number: 20190247346Abstract: A use of a poultry crude protein extract for preparing an anti-fatigue composition is provided. The poultry crude protein extract is obtained by extraction of poultry meat at high temperature and high pressure and the removal of fat by oil and water separation, and the poultry crude protein extract includes at least branched-chain amino acid (BCAA), histidine, threonine, lysine, and phenylalanine, wherein anti-fatigue entails increasing muscle glycogen concentration, helping to increase exercise tolerance, helping to increase blood urea nitrogen metabolism, and helping to inhibit lactic acid production.Type: ApplicationFiled: January 21, 2019Publication date: August 15, 2019Applicant: Yuan Jin Chuang Enterprise Co.,LtdInventors: Hung-Yuan Wu, Meng-Hui Lin
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Patent number: 8966372Abstract: A method is implemented in a video playback system that includes a video editing interface for assigning geotagging data to a video. The method comprises receiving, by the video playback system, the video from a tangible storage medium. The method further comprises reading metadata associated with the video, selecting a frame from the video, providing a user interface with a map, displaying a default location of the selected frame on the map according to the metadata, receiving geotagging data via the user interface, and associating the geotagging data with the selected frame of the video to generate a geo-based timeline.Type: GrantFiled: February 10, 2011Date of Patent: February 24, 2015Assignee: Cyberlink Corp.Inventors: Meng Hui Lin, Huang-Hsin Wu
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Publication number: 20120210227Abstract: A method is implemented in a video playback system that includes a video editing interface for assigning geotagging data to a video. The method comprises receiving, by the video playback system, the video from a tangible storage medium. The method further comprises reading metadata associated with the video, selecting a frame from the video, providing a user interface with a map, displaying a default location of the selected frame on the map according to the metadata, receiving geotagging data via the user interface, and associating the geotagging data with the selected frame of the video to generate a geo-based timeline.Type: ApplicationFiled: February 10, 2011Publication date: August 16, 2012Applicant: CYBERLINK CORP.Inventor: Meng Hui Lin
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Patent number: 6541871Abstract: A method for fabricating a stacked chip package comprises the steps of: (a) attaching a first semiconductor chip to an upper surface of a substrate through a first adhesive layer; (b) partially curing the first adhesive layer such that it gels but does not harden; (c) attaching a second semiconductor chip to the first semiconductor chip through a second adhesive layer; (d) curing the first and second adhesive layer; (e) electrically coupling the first and second semiconductor chips to a structure for making external electrical connection provided on the substrate; and (f) forming a package body over the first semiconductor chip, the second semiconductor chip, and a portion of the upper surface of the substrate. Since the first and second adhesive layers may be cured in one single step, the cycle time may be reduced thereby cutting down the production cost.Type: GrantFiled: March 18, 2002Date of Patent: April 1, 2003Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Tsung-Ming Pai, Chung-Hao Lee, Pao-Hei Chang Chin, Meng-Hui Lin, Song-Fei Wang
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Publication number: 20020094605Abstract: A method for fabricating a stacked chip package comprises the steps of: (a) attaching a first semiconductor chip to an upper surface of a substrate through a first adhesive layer; (b) partially curing the first adhesive layer such that it gels but does not harden; (c) attaching a second semiconductor chip to the first semiconductor chip through a second adhesive layer; (d) curing the first and second adhesive layer; (e) electrically coupling the first and second semiconductor chips to a structure for making external electrical connection provided on the substrate; and (f) forming a package body over the first semiconductor chip, the second semiconductor chip, and a portion of the upper surface of the substrate. Since the first and second adhesive layers may be cured in one single step, the cycle time may be reduced thereby cutting down the production cost.Type: ApplicationFiled: March 18, 2002Publication date: July 18, 2002Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tsung-Ming Pai, Chung-Hao Lee, Pao-Hei Chang Chin, Meng-Hui Lin, Song-Fei Wang
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Patent number: 6387728Abstract: A method for fabricating a stacked chip package comprises the steps of: (a) attaching a first semiconductor chip to an upper surface, of a substrate through a first adhesive layer; (b) partially curing the first adhesive layer such that it gels but does not harden; (c) attaching a second semiconductor chip to the first semiconductor chip through a second adhesive layer; (d) curing the first and second adhesive layer; (e) electrically coupling the first and second semiconductor chips to a structure for making external electrical connection provided on the substrate; and (f) forming a package body over the first semiconductor chip, the second semiconductor chip, and a portion of the upper surface of the substrate. Since the first and second adhesive layers may be cured in one single step the cycle time may be reduced thereby cutting down the production cost.Type: GrantFiled: May 2, 2000Date of Patent: May 14, 2002Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Tsung-Ming Pai, Chung-Hao Lee, Pao-Hei Chang Chin, Meng-Hui Lin, Song-Fei Wang
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Patent number: 6300166Abstract: A method for packaging a BGA and the structure of the BGA for using the method are disclosed. The structure of the substrate of the BGA includes multiple pairs of aligned slots (11, 12) defined along the X-axis thereof, and a passage (13) corresponding to and perpendicular to one pair of aligned slots (11, 12). While using the method to package the substrate, one side of the substrate will be entirely covered by a first protective layer to protect the chips and the other side of the substrate will form multiple lines of a second protective layers to protect the bonding wires.Type: GrantFiled: August 30, 1999Date of Patent: October 9, 2001Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Su Tao, Yu-Ching Tsai, Meng-Hui Lin, Chin-Ming Chung
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Patent number: 6215193Abstract: A multichip module includes a substrate having two padding strips, a first chip, and a second chip mounted thereon. The padding strips are mounted to two sides of the first chip. The second chip is disposed above the first chip in a manner that the bonding pads of the first chip are exposed outside the lateral edges of the second chip. In another embodiment of the invention, the substrate includes a recess, a first chip, and a second chip. The first chip is received in the first chip, and the second chip is disposed above the first chip in a manner that the bonding pads of the first chip are exposed outside the lateral edges of the second chip. A method is provided to manufacture a multichip module by placing a first chip on a substrate and then placing a second chip above the first chip in a manner that the bonding pads of the first chip are exposed outside the lateral edges of the second chip.Type: GrantFiled: April 21, 1999Date of Patent: April 10, 2001Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Su Tao, Meng-Hui Lin
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Patent number: 6161753Abstract: A stacked dies include a substrate, a lower chip and an upper chip. A plurality of upper wires have the bent portion at the bonding pad of the substrate to reduce the height and increase the strength of the wire so as to increase the reliability of the product and to increase the space between the lower wire and the upper wire for reduction cross talk. A method of making low profile upper wire connection comprising steps of: after an upper wire is connected to a first bonding point, a capillary is moved straight up a first distance, and then the capilairy is moved away from a second bonding point thus making a first reverse action to bend the wire in an appropriate angle so as to form the first bent point. The capillary is again raised a second distance and moved downward a second reverse action to bend the upper wire by an appropriate angle so as to form the second bent point.Type: GrantFiled: November 1, 1999Date of Patent: December 19, 2000Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yu-Fang Tsai, Sung-Fei Wang, Su Tao, Meng-Hui Lin