Abstract: A method of forming a landed polysilicon plug in a self-aligned contact. A substrate having a plurality of gate electrodes thereon is provided. Before forming the self-aligned contact window, a dielectric liner layer conformal to a surface profile of the substrate and the gate electrodes is formed. An inter-layer dielectric layer is next formed over the dielectric liner layer. High etching selectivity ratio between the inter-layer dielectric layer and the dielectric liner layer is chosen, and thus the dielectric liner layer is used as an etching stop layer in the process of etching out the self-aligned contact window. After a polysilicon layer that fills the self-aligned contact window and covers the dielectric layer is formed, planarization is carried out to form the landed polysilicon plug having a desired thickness.

Abstract: A method for making interlevel contacts having low contact resistance (Rc) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi2) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide inter connecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon-layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings.

Abstract: The invention has two embodiments for forming a contact plug having large nail shaped landing pad. The large pad areas increase the overlay tolerances. The first embodiment comprises forming first 20 and second 24 insulating layers over a semiconductor structure. A first photoresist layer 28 with a first opening is formed over the second insulating layer 24. The second insulating layer 24 is isotropically etched using an etchant with a high selectivity thereby forming a disk shaped opening 26A. The disk shaped opening is used to define the large nail shaped landing pad. The first insulating layer 20 is etched using a dry etch thereby forming a nail shaped contact opening 26. The opening is filled with polysilicon to form the nail shaped conductive plug 36. The second embodiment begins by forming a first insulating layer 40 over a semiconductor structure. A first photoresist layer 44 with a first opening is formed over the first insulating layer 24.

Abstract: A method for reducing a contact resistance is described. The method is suitable for a wafer that comprises a WSix layer, a native oxide on the WSix layer, and a dielectric layer surrounding and partially covering the WSix layer, wherein the dielectric layer has a contact hole exposing the native oxide. The wafer is placed into a vacuum system. A first polysilicon layer is deposited on the native oxide. The first polysilicon layer and the native oxide are annealed. A second polysilicon layer is formed on the WSix. The wafer is removed from a vacuum system.

Abstract: The invention describes a self-aligned etching process. A conductive layer and a first insulating layer are formed on a substrate in sequence, and then the conductive layer and the first insulating layer are patterned to form a plurality of stacks on desired regions. Subsequently, spacers are formed on sidewalls of each stack, and a stop layer is then formed on the substrate. A second insulating layer is formed on the substrate and is planarized. Portions of the second insulating layer are removed to form a plurality of openings and to expose portions of the stop layer located between spacers. The exposed stop layer is removed.

Abstract: A twin bit DRAM cell capable of storing two bits of digital data as stored charge within the DRAM cell is disclosed. The twin bit DRAM cell has two pass transistors, a trench capacitor, and a stack capacitor. The pass transistors each have a source connected to a bit line voltage generator to control placement of the charge within the twin bit DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. The trench capacitor has a top plate connected to the drain of the first pass transistor and a bottom plate connected to a first biasing voltage source. The stack capacitor has a first plate connected to the drain of the second pass transistor and a second plate connected to a second biasing voltage generator. Twin bit DRAM cells will be arranged in a plurality of rows and columns to form an array of twin bit DRAM cells.

Abstract: A method of fabricating a capacitor is described in which a substrate comprises a transistor and a planarized insulation layer. An opening is formed in the insulation layer, exposing one of the source/drain of the transistor. A sacrificial plug is formed in the first opening. The insulation layer surrounding the first opening is removed to form a second opening and a certain thickness of the insulation layer is retained at the bottom of the second opening. The sacrificial plug is removed and simultaneously forming a node plug and a first electrode respectively in the first opening and on the bottom and side wall of the second opening. A dielectric layer is further formed on the surface of the first electrode and a second electrode is formed on the dielectric layer.

Abstract: A method for making interlevel contacts having low contact resistance (R.sub.c) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi.sub.2) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide interconnecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings.

Abstract: A new and improved method for fabricating planarized isolation trenches, wherein erosion of insulating material at the edges of trenches is surpressed without sacrificing a minimal width of the isolation trench, has been developed. The process fabricates sidewall spacers before etching the isolation trench into the semiconductor substrate. After filling the etched trench with insulating material and plartarization of the insulating material, the sidewall spacers protect the insulating material filling the trench and prevent the formation of "divots" at the edges of the trench. Since the spacers are formed prior to the etching of the trench in the semiconductor substrate, a minimal width of the isolation trench can be maintained and less area is required for the isolation trench.

Abstract: A method for forming a DRAM cell of a DRAM circuit is disclosed. The DRAM circuit includes a periphery region and a cell region. The DRAM cell is in the cell region and comprises an access transistor and a capacitor. The access transistor has a gate, a source, and a drain. The periphery region includes a plurality of gates. The method comprises the deposition of a silicon oxynitride layer over the gates, the silicon oxynitride layer acting as a bottom anti-reflection coating. That portion of the silicon oxynitride layer that lies over the DRAM cell is removed. A landing pad is formed over the source of the access transistor and a bitline pad is formed over the drain of the transistor. Next, a first oxide layer is formed over the landing pad and the bitline pad. A capacitor is formed over the landing pad and a second oxide layer is formed over the capacitor.

Abstract: A method for making a planarized capacitor-over-bit lines structure on dynamic random access memory devices was achieved. After forming the array of FETs for the memory cells, a first polysilicon layer is deposited and patterned to simultaneously form bit lines and polysilicon landing pads that also form the node contacts for stacked capacitors. A thick first insulating layer is deposited and planarized. Node contact openings are etched in the first insulating layer to the landing pads and a thin second polysilicon layer is deposited which also fills the contact openings. Trenches are etched through the second polysilicon layer and into the first insulating layer around the desired capacitor areas while protecting the remaining DRAM chip area from etching. A thin third polysilicon layer is deposited and etched back to form sidewall spacers and to form capacitor bottom electrodes with increased capacitance.

Abstract: A metal layer (24) is formed on an isolation layer (22) to act as interconnections. Subsequently, a thin liner layer (26) is optionally formed along the surface of the metal layer (24) to serve as a buffer layer. An undoped silicate glass (USG) layer (28) is deposited on the liner layer (26). The USG layer (28) is formed using ozone and tetraethylorthosilicate (TEOS) as a source at a temperature of approximately 380 to 420.degree. C. Oxygen gas is used as a carrier for the ozone. The flow rate of the oxygen gas is approximately 4000 to 6000 sccm. Helium gas is used as a carrier for the TEOS. The flow rate of the helium is approximately 3000 to 5000 sccm. A silicon nitride layer (30) is deposited on the USG layer (28) using plasma enhanced chemical vapor deposition (PECVD). The silicon nitride layer (30) serves as a main passivation layer. The thickness of the silicon nitride layer (30) is approximately 3000 to 7000 angstroms.

Abstract: A twin bit DRAM cell capable of storing two bits of digital data as stored charge within the DRAM cell is disclosed. The twin bit DRAM cell has two pass transistors, a trench capacitor, and a stack capacitor. The pass transistors each have a source connected to a bit line voltage generator to control placement of the charge within the twin bit DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. The trench capacitor has a top plate connected to the drain of the first pass transistor and a bottom plate connected to a first biasing voltage source. The stack capacitor has a first plate connected to the drain of the second pass transistor and a second plate connected to a second biasing voltage generator. Twin bit DRAM cells will be arranged in a plurality of rows and columns to form an array of twin bit DRAM cells.

Abstract: A method is described for forming capacitor plates with extended surface area using polysilicon hemispherical grains or HSG polysilicon. The HSG polysilicon is formed on the top surface and sidewalls of first capacitor plates. A vertical anisotropic etching step forms an irregular top surface of the first capacitor plates and an anneal step provides good adhesion between the grains of HSG polysilicon and the sidewalls of the first capacitor plates. A timed etchback of the dielectric between the first capacitor plates insures good electrical insulation between adjacent first capacitor plates.

Abstract: A method for fabricating very narrow contacts on semiconductor substrate for increasing the packing density of devices on Ultra Large Scale Integration (ULSI) circuits was achieved. The method involves using conventional photolithographic techniques and anisotropic plasma etching to etch openings in a conducting layer and partially etch into an underlying planar insulating layer that covers and isolates the devices and device contact areas. Another conformal conducting layer is deposited on the substrate and in the openings and then etched back to form sidewall spacers in the openings. Using the original conducting layer and the sidewall spacers as an etch mask, the planar insulating layer is anisotropically etched within the sidewall spacers to form very narrow (small) contact opening to the desired device contact areas.

Abstract: A method for making memory cells having self-aligned node contacts to bit lines was achieved. After forming the array of FETs for the memory cells, a first insulating layer is deposited and planarized. A single masking step is used to concurrently etch bit lines and node contact openings for crown capacitors. A second polysilicon layer and a silicide layer are deposited to form a polycide layer which is specially patterned to form bit lines with portions of the polycide layer extending over the node contacts. A second insulating layer (e.g., BPSG) is deposited and openings are etched aligned over the node contacts to the polycide. The polycide is selectively etched in the openings to electrically isolate the individual bit lines and concurrently form self-aligned node contacts. A third insulating layer is deposited and etched back to form insulating sidewall liners on the bit lines.

Abstract: A method for fabricating small contact openings in the polysilicon/metal 1 dielectric (PMD) layer on semiconductor substrates using polymer sidewall spacers was achieved. This extends the current photoresist resolution limits while simplifying the manufacturing process. The method involves depositing a polysilicon layer on the PMD layer and using a photoresist mask having openings over device contact areas in the substrate. The polysilicon layer is then patterned to form openings with vertical sidewalls to the PMD insulating layer. The contact openings are then anisotropically plasma etched in a gas mixture that simultaneously forms polymer sidewall spacers on the sidewalls in the openings in the polysilicon layer. These sidewall spacers further reduce the contact opening size. The remaining photoresist layer and polymer sidewall spacers are simultaneously removed to complete the narrow contact openings. This method eliminates the need to use an additional deposition and etch-back step to form the sidewalls.

Abstract: A method of fabricating double and multi-cylindrical storage capacitors is provided. To form a double crown capacitor, a conductive layer is formed on a multi-layer gate and insulation structure. The conductive layer includes a portion extending through a contact hole provided in the underlying insulation structure to thereby electrically connect the conductive layer with an active region of a transistor. A groove is formed in the conductive layer defining an area for a plurality of separated electrodes. First spacers are formed on the side walls of the groove. Then, the conductive layer is anisotrophically etched using the spacers as an etch mask thus forming an annular ridge around the area where the memory device is formed. The first spacers are then removed. Second and third spacers are then formed on the both sidewalls of the annular ridge.

Abstract: A method for manufacturing an array of dynamic random access memory (DRAM) cells having a single crown-shaped or a double crown-shaped stacked capacitors is accomplished. The method involves forming an array of device areas on a silicon substrate in which FETs for the DRAM cells are formed. After forming bit line contacts and bit line metallurgy contacting one of the two source/drain areas of each FET, a thick low melting temperature glass (BPSG) is deposited and planarized by annealing. Node capacitor contact openings are formed in the BPSG using a polysilicon sidewall method that reduces the contact size, and a thick polysilicon layer is deposited to contact the node source/drain areas of the FETs, and also provides a planar polysilicon surface. A specially designed edge phase-shift mask is then used with a positive photoresist to pattern the thick polysilicon layer and form crown-shaped bottom electrodes.

Abstract: A method is provided for fabricating a single crown electrode for a capacitor for semiconductor memory devices. A conductive layer is formed over a multi-layer gate and insulation structure. The conductive layer includes a portion extending through a contact hole to thereby electrically connect the conductive layer with an active region of a transistor formed in the substrate Next, a novel groove is etched in the conductive layer between adjacent memory cells. Sidewall spacers are formed on the groove. The conductive layer is anisotropically etched using the spacers as an etching mask, thereby forming a plurality of electrodes having upright portions. The etching exposes the first insulation layer in the area under the grooves, but leaves a thickness of the base conductive layer to form the bottom of the electrode. The spacers then are removed and a conformal dielectric layer is formed over the surface. Lastly, a top plate electrode is formed over the conformal dielectric layer.