Patents by Inventor Meng-Jia Lin
Meng-Jia Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10773953Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.Type: GrantFiled: September 7, 2017Date of Patent: September 15, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Meng-Jia Lin, Yung-Hsiao Lee, Weng-Yi Chen, Shih-Wei Li, Chung-Hsien Liu
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Patent number: 9905711Abstract: An avalanche photodetector device includes a substrate having a front side and a back side, an avalanche photo detector structure disposed on the front side of the substrate, a plurality of heat sinks disposed on the back side of the substrate, and a plurality of reflecting islands disposed on the back side of the substrate.Type: GrantFiled: April 15, 2016Date of Patent: February 27, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tzung-Han Tan, Chang-Sheng Hsu, Meng-Jia Lin, Te-Huang Chiu
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Publication number: 20170362081Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.Type: ApplicationFiled: September 7, 2017Publication date: December 21, 2017Inventors: Meng-Jia Lin, Yung-Hsiao Lee, Weng-Yi Chen, Shih-Wei Li, Chung-Hsien Liu
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Patent number: 9790088Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.Type: GrantFiled: January 12, 2016Date of Patent: October 17, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Meng-Jia Lin, Yung-Hsiao Lee, Weng-Yi Chen, Shih-Wei Li, Chung-Hsien Liu
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Publication number: 20170271529Abstract: An avalanche photodetector device includes a substrate having a front side and a back side, an avalanche photo detector structure disposed on the front side of the substrate, a plurality of heat sinks disposed on the back side of the substrate, and a plurality of reflecting islands disposed on the back side of the substrate.Type: ApplicationFiled: April 15, 2016Publication date: September 21, 2017Inventors: Tzung-Han Tan, Chang-Sheng Hsu, Meng-Jia Lin, Te-Huang Chiu
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Publication number: 20170166441Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.Type: ApplicationFiled: January 12, 2016Publication date: June 15, 2017Inventors: Meng-Jia Lin, Yung-Hsiao Lee, Weng-Yi Chen, Shih-Wei Li, Chung-Hsien Liu
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Publication number: 20160229692Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a base substrate and a MEMS structure. The base substrate comprises a CMOS structure. The MEMS structure is formed on the base substrate adjacent to the CMOS structure. The MEMS structure is connected to the CMOS structure. The MEMS structure comprises a membrane and a backplate. The base substrate has a cavity corresponding to the MEMS structure.Type: ApplicationFiled: March 10, 2015Publication date: August 11, 2016Inventors: Yuan-Sheng Lin, Chang-Sheng Hsu, Meng-Jia Lin, Shih-Wei Li, Yan-Da Chen
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Patent number: 9150407Abstract: A method for fabricating a microelectromechanical system (MEMS) device of the present invention includes the following steps: providing a substrate, comprising a circuit region and a MEMS region separated from each other; forming an interconnection structure on the substrate in the circuit region, and simultaneously forming a plurality of dielectric layers and a first electrode on the substrate in the MEMS region, wherein the first electrode comprises at least two metal layers formed in the dielectric layers and a protection ring formed in the dielectric layers and connecting two adjacent metal layers, so as to define an enclosed space between the two adjacent metal layers; forming a second electrode on the first electrode; and removing the dielectric layers outside the enclosed space in the MEMS region to form a cavity between the electrodes.Type: GrantFiled: July 18, 2013Date of Patent: October 6, 2015Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Tzung-Han Tan, Bang-Chiang Lan, Ming-I Wang, Chien-Hsin Huang, Meng-Jia Lin
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Patent number: 8981501Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.Type: GrantFiled: April 25, 2013Date of Patent: March 17, 2015Assignee: United Microelectronics Corp.Inventors: Meng-Jia Lin, Chang-Sheng Hsu, Kuo-Hsiung Huang, Wei-Hua Fang, Shou-Wei Hsieh, Te-Yuan Wu, Chia-Huei Lin
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Publication number: 20140319693Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.Type: ApplicationFiled: April 25, 2013Publication date: October 30, 2014Applicant: United Microelectronics Corp.Inventors: Meng-Jia Lin, Chang-Sheng Hsu, Kuo-Hsiung Huang, Wei-Hua Fang, Shou-Wei Hsieh, Te-Yuan Wu, Chia-Huei Lin
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Patent number: 8710601Abstract: A micro electro mechanical system (MEMS) structure is disclosed. The MEMS structure includes a backplate electrode and a 3D diaphragm electrode. The 3D diaphragm electrode has a composite structure so that a dielectric is disposed between two metal layers. The 3D diaphragm electrode is adjacent to the backplate electrode to form a variable capacitor together.Type: GrantFiled: November 19, 2009Date of Patent: April 29, 2014Assignee: United Microelectronics Corp.Inventors: Chien-Hsin Huang, Bang-Chiang Lan, Ming-I Wang, Hui-Min Wu, Tzung-I Su, Chao-An Su, Tzung-Han Tan, Min Chen, Meng-Jia Lin
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Patent number: 8642986Abstract: An integrated circuit (IC) having a microelectromechanical system (MEMS) device buried therein is provided. The integrated circuit includes a substrate, a metal-oxide semiconductor (MOS) device, a metal interconnect, and the MEMS device. The substrate has a logic circuit region and a MEMS region. The MOS device is located on the logic circuit region of the substrate. The metal interconnect, formed by a plurality of levels of wires and a plurality of vias, is located above the substrate to connect the MOS device. The MEMS device is located on the MEMS region, and includes a sandwich membrane located between any two neighboring levels of wires in the metal interconnect and connected to the metal interconnect.Type: GrantFiled: September 23, 2009Date of Patent: February 4, 2014Assignee: United Microelectronics Corp.Inventors: Tzung-Han Tan, Bang-Chiang Lan, Ming-I Wang, Tzung-I Su, Chien-Hsin Huang, Hui-Min Wu, Chao-An Su, Min Chen, Meng-Jia Lin
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Publication number: 20130302933Abstract: A microelectromechanical system (MEMS) device and a method for fabricating the same are described. The method of the present invention includes the following steps. A substrate is provided, including a circuit region and a MEMS region separated from each other. An interconnection structure is formed on the substrate in the circuit region, and simultaneously a plurality of dielectric layers and a first electrode are formed on the substrate in the MEMS region. The first electrode includes at least two metal layers and a protection ring. The metal layers and the protection ring are formed in the dielectric layers. The protection ring connects two adjacent metal layers, so as to define an enclosed space between the two adjacent metal layers. A second electrode is formed on the first electrode. The dielectric layers outside the enclosed space in the MEMS region are removed to form a cavity between the electrodes.Type: ApplicationFiled: July 18, 2013Publication date: November 14, 2013Inventors: Tzung-Han TAN, Bang-Chiang Lan, Ming-I Wang, Chien-Hsin Huang, Meng-Jia Lin
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Patent number: 8558336Abstract: A semiconductor photodetector structure is provided. The structure includes a substrate, a photodetecting element and a semiconductor layer disposed on the photodetecting element. The substrate includes a first semiconductor material and includes a deep trench. The surface of the deep trench includes a first type dopant. The photodetecting element is disposed in the deep trench. The photodetecting element includes a second semiconductor material. The semiconductor layer includes a second type dopant.Type: GrantFiled: August 17, 2009Date of Patent: October 15, 2013Assignee: United Microelectronics Corp.Inventors: Tzung-I Su, Bang-Chiang Lan, Chao-An Su, Hui-Min Wu, Ming-I Wang, Chien-Hsin Huang, Tzung-Han Tan, Min Chen, Meng-Jia Lin, Wen-Yu Su
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Patent number: 8525389Abstract: A microelectromechanical system (MEMS) device and a method for fabricating the same are described. The MEMS device includes a first electrode and a second electrode. The first electrode is disposed on a substrate, and includes at least two metal layers, a first protection ring and a dielectric layer. The first protection ring connects two adjacent metal layers, so as to define an enclosed space between two adjacent metal layers. The dielectric layer is disposed in the enclosed space and connects two adjacent metal layers. The second electrode is disposed on the first electrode, wherein a cavity is formed between the first electrode and the second electrode.Type: GrantFiled: November 10, 2010Date of Patent: September 3, 2013Assignee: United Microelectronics Corp.Inventors: Tzung-Han Tan, Bang-Chiang Lan, Ming-I Wang, Chien-Hsin Huang, Meng-Jia Lin
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Patent number: 8502382Abstract: A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.Type: GrantFiled: April 30, 2012Date of Patent: August 6, 2013Assignee: United Microelectronics Corp.Inventors: Bang-Chiang Lan, Ming-I Wang, Hui-Min Wu, Min Chen, Chien-Hsin Huang, Tzung-I Su, Chao-An Su, Tzung-Han Tan, Li-Che Chen, Meng-Jia Lin
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Patent number: 8460960Abstract: A method for fabricating integrated circuit is provided. First, a first interconnect structure including a plurality of first dielectric layers and a plurality of first conductive patterns stacked therewith alternately is formed on a MEMS region of a conductive substrate. Next, an interlayer is formed on the first interconnect structure and covering the first conductive patterns. Next, a poly silicon mask layer corresponding to the first conductive patterns is formed on the interlayer and exposing a portion of the media layer. Next, the portion of the interlayer exposed by the poly silicon mask layer and a portion of the first dielectric layer corresponding thereto are removed to form a plurality of openings. Then, a portion of the conductive substrate in the MEMS region is removed.Type: GrantFiled: July 20, 2011Date of Patent: June 11, 2013Assignee: United Microelectronics Corp.Inventors: Meng-Jia Lin, Bang-Chiang Lan, Ming-I Wang, Chien-Hsin Huang
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Publication number: 20130056858Abstract: A method for fabricating integrated circuit is provided. First, a substrate having a micro electromechanical system (MEMS) region is provided. A first interconnect structure and a hard mask layer have been disposed on the MEMS region in sequence. Next, an anisotropic etching process is performed by using the hard mask layer as a photo mask to etch a portion of the first interconnect structure exposed by the hard mask layer. Accordingly, a MEMS structure is formed. A portion of the substrate in MEMS region is exposed by the MEMS structure. Then, an isotropic etching process is performed for removing the portion of the substrate in MEMS region to form a cavity with a center region and a ring-like indentation region. The center region is surrounded by the ring-like indentation region and the MEMS structure suspends above the cavity. An integrated circuit is also provided.Type: ApplicationFiled: September 1, 2011Publication date: March 7, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Tian-You DING, Meng-Jia LIN, Chin-Sheng YANG
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Patent number: 8384214Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a dielectric layer, a pad structure and a protection structure. The dielectric layer is disposed on the substrate. The pad structure is disposed in the dielectric layer. The pad structure includes a plurality of first metal layers and a plurality of plugs which are electrically connected to each other vertically. There is no contact plug disposed between the pad structure and the substrate. The protection structure is disposed in the dielectric layer and encompasses the pad structure.Type: GrantFiled: October 13, 2009Date of Patent: February 26, 2013Assignee: United Microelectronics Corp.Inventors: Hui-Min Wu, Bang-Chiang Lan, Ming-I Wang, Tzung-I Su, Chien-Hsin Huang, Chao-An Su, Tzung-Han Tan, Min Chen, Meng-Jia Lin
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Publication number: 20130023081Abstract: A method for fabricating integrated circuit is provided. First, a first interconnect structure including a plurality of first dielectric layers and a plurality of first conductive patterns stacked therewith alternately is formed on a MEMS region of a conductive substrate. Next, an interlayer is formed on the first interconnect structure and covering the first conductive patterns. Next, a poly silicon mask layer corresponding to the first conductive patterns is formed on the interlayer and exposing a portion of the media layer. Next, the portion of the interlayer exposed by the poly silicon mask layer and a portion of the first dielectric layer corresponding thereto are removed to form a plurality of openings. Then, a portion of the conductive substrate in the MEMS region is removed.Type: ApplicationFiled: July 20, 2011Publication date: January 24, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Meng-Jia LIN, Bang-Chiang Lan, Ming-I Wang, Chien-Hsin Huang