Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Abstract: A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.

Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

Abstract: A processing system is adapted to execute a method for testing power leakage of a circuit. The method includes: obtaining a plurality of undefined nets according to a netlist and power mode information; obtaining a trace path according to the undefined nets and the power mode information; and determining whether there is a risk of power leakage in the trace path, and outputting a testing result.

Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

Abstract: A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.

Abstract: A method of detecting the relations between the pins of a circuit and a computer program product thereof are provided. The method includes: retrieving a circuit description file describing a circuit; retrieving at least one data pin and at least one clock pin of the circuit; converting the circuit to a cell level; and tracing the circuit in the cell level to identify multiple flip-flops coupled to the clock pin; tracing the circuit in the cell level to identify a target flip-flop coupled to the data pin; and determining whether the data pin is related to the clock pin according to the data signal and the clock signal of the target flip-flop.

Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

Abstract: A method of detecting the relations between the pins of a circuit and a computer program product thereof are provided. The method includes: retrieving a circuit description file describing a circuit; retrieving at least one data pin and at least one clock pin of the circuit; converting the circuit to a cell level; and tracing the circuit in the cell level to identify multiple flip-flops coupled to the clock pin; tracing the circuit in the cell level to identify a target flip-flop coupled to the data pin; and determining whether the data pin is related to the clock pin according to the data signal and the clock signal of the target flip-flop.

Abstract: A checking method for checking whether a signal in a chip is interference-free, and the checking method includes the following operations: analyzing, by a processor, a netlist file to acquire a first node for outputting the signal in the chip, in which the netlist file is configured to describe a circuit architecture of the chip; searching, by the processor, candidate nodes associated with the signal according to the netlist file and the first node; and determining, by the processor, whether a first candidate node of the candidate nodes is connected to an anti-interference circuit, in order to check whether the signal is interference-free.

Abstract: This invention discloses a circuit encoding method and a circuit structure recognition method. The circuit encoding method is applied to a circuit structure recognition process of a circuit. The circuit is coupled to a voltage source and a reference voltage. The circuit encoding method includes: selecting a target transistor from the circuit; when a terminal of the target transistor is electrically connected to the voltage source or the reference voltage, adding a first value to a terminal value of the terminal; when the terminal of the target transistor is electrically connected to a terminal other than the voltage source and the reference voltage, adding a second value to the terminal value of the terminal; and taking a set of multiple terminal values of the target transistor as a transistor signature of the target transistor.

Abstract: A checking method for checking whether a signal in a chip is interference-free, and the checking method includes the following operations: analyzing, by a processor, a netlist file to acquire a first node for outputting the signal in the chip, in which the netlist file is configured to describe a circuit architecture of the chip; searching, by the processor, candidate nodes associated with the signal according to the netlist file and the first node; and determining, by the processor, whether a first candidate node of the candidate nodes is connected to an anti-interference circuit, in order to check whether the signal is interference-free.

Abstract: This invention discloses a circuit encoding method and a circuit structure recognition method. The circuit encoding method is applied to a circuit structure recognition process of a circuit. The circuit is coupled to a voltage source and a reference voltage. The circuit encoding method includes: selecting a target transistor from the circuit; when a terminal of the target transistor is electrically connected to the voltage source or the reference voltage, adding a first value to a terminal value of the terminal; when the terminal of the target transistor is electrically connected to a terminal other than the voltage source and the reference voltage, adding a second value to the terminal value of the terminal; and taking a set of multiple terminal values of the target transistor as a transistor signature of the target transistor.

Abstract: An integrated circuit test model is generated according to a circuit connection net-list, an isolation cell topology, and a pin voltage information spec file, so that the procedure of generating the integrated circuit test model can be time-saving, efficient, and fool-proof. Besides, while tracing a current path of a node of the circuit connection net-list, the generated integrated circuit test model can be more precise if certain limitations are added.

Abstract: The present invention relates to an extracting method for a circuit model, configured to represent output driving capability and an input capacitor of an interface pin of an application circuit. The extracting method comprises: receiving a netlist describing a circuit structure of the application circuit, which comprises a plurality of transistors; selecting an interface pin of the application circuit in the netlist; selecting a bias pin of the application circuit in the netlist; selecting at least one path between the interface pin and the bias pin in the netlist; and obtaining sum of equivalent width/length ratios according to the width/length ratios of all first transistors coupled to the at least one path.

Abstract: The present invention relates to an extracting method for a circuit model, configured to represent output driving capability and an input capacitor of an interface pin of an application circuit. The extracting method comprises: receiving a netlist describing a circuit structure of the application circuit, which comprises a plurality of transistors; selecting an interface pin of the application circuit in the netlist; selecting a bias pin of the application circuit in the netlist; selecting at least one path between the interface pin and the bias pin in the netlist; and obtaining sum of equivalent width/length ratios according to the width/length ratios of all first transistors coupled to the at least one path.