Abstract: A prediction processing system includes a processing circuit and a reference data buffer. The processing circuit performs a first inter prediction operation upon a first prediction block in a frame to generate a first inter prediction result, and further performs a second inter prediction operation upon a second prediction block during a first period. The reference data buffer buffers a reference data derived from the first inter prediction result. The processing circuit further fetches the reference data from the reference data buffer, and performs a non-inter prediction operation according to at least the reference data during a second period, wherein the second period overlaps the first period.

Abstract: A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data.

Abstract: A prediction processing system includes a processing circuit and a reference data buffer. The processing circuit performs a first inter prediction operation upon a first prediction block in a frame to generate a first inter prediction result, and further performs a second inter prediction operation upon a second prediction block during a first period. The reference data buffer buffers a reference data derived from the first inter prediction result. The processing circuit further fetches the reference data from the reference data buffer, and performs a non-inter prediction operation according to at least the reference data during a second period, wherein the second period overlaps the first period.

Abstract: A video decoder has a plurality of processing circuits, including a first processing circuit and a second processing circuit. The first processing circuit applies a first decoding process to a current coding block according to reconstructed neighbor samples, and has a local neighbor buffer for buffering the reconstructed neighbor samples used by the first decoding process. The second processing circuit applies a second decoding process to the current coding block according to at least a portion of the reconstructed neighbor samples retrieved from the local neighbor buffer, wherein the second decoding process is different from the first decoding process.

Abstract: A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data.

Abstract: A video decoding method is used for decoding a multi-plane video bitstream. The multi-plane video bitstream includes a first video subset bitstream corresponding to a fundamental plane (FP) and at least one second video subset bitstream corresponding to at least one augmented plane (AP). The video decoding method includes decoding the first video subset bitstream, decoding the at least one second video subset bitstream, and performing resampling of one decoded FP frame to generate one resampled frame. Decoding the first video subset bitstream includes performing decoding of a first FP frame to generate a first decoded FP frame. Decoding the at least one second video subset bitstream includes performing decoding of a first AP frame to generate a first decoded AP frame. A processing time of performing decoding of the first FP frame overlaps a processing time of performing resampling of said one decoded FP frame.

Abstract: A video processing apparatus includes a reconstruct circuit, a storage device, and an intra prediction circuit. The reconstruct circuit generates reconstructed pixels of a first block of a picture. The storage device at least stores a portion of the reconstructed pixels of the first block, wherein a capacity of the storage device is smaller than a reconstructed data size of the picture. The intra prediction circuit performs intra prediction of a second block of the picture based at least partly on pixel data obtained from the storage device.

Abstract: One exemplary video processing apparatus includes a control circuit and a size selection circuit. The control circuit determines picture boundary information. The size selection circuit refers to at least the picture boundary information to select a size for a block associated with encoding of a picture, wherein selection of the size is constrained by the picture boundary information to ensure that the block with the selected size is not across a picture boundary of the picture.

Abstract: An apparatus for multi-standard Intra prediction decoding in a video decoder for decoding two video streams coded in two different video coding standards is disclosed. The apparatus comprises a first Intra prediction decoder to decode a first bitstream comprising one or more first Intra prediction coded blocks, and a second Intra prediction decoder to decode a second bitstream comprising one or more second Intra prediction coded blocks. The first Intra prediction coded blocks are coded according to a first video coding standard and the second Intra prediction coded blocks are coded according to a second video coding standard. The first Intra prediction decoder and the second Intra prediction decoder are arranged to perform Intra prediction decoding on the two video streams simultaneously by decoding the two video streams in an interleaved manner at a picture level, slice level, or largest coding unit (LCU)/macroblock (MB) level.

Abstract: A video processing apparatus includes a first processing circuit, a second processing circuit, and a control circuit. The first processing circuit performs a first processing operation. The second processing circuit performs a second processing operation different from the first processing operation. The control circuit generates at least one output coding unit to the second processing circuit according to an input coding unit generated from the first processing circuit, wherein the control circuit checks a size of the input coding unit to selectively split the input coding unit into a plurality of output coding units.

Abstract: One exemplary video processing apparatus includes a control circuit and a size selection circuit. The control circuit determines picture boundary information. The size selection circuit refers to at least the picture boundary information to select a size for a block associated with encoding of a picture, wherein selection of the size is constrained by the picture boundary information to ensure that the block with the selected size is not across a picture boundary of the picture.

Abstract: A video processing apparatus includes a reconstruct circuit, a storage device, and an intra prediction circuit. The reconstruct circuit generates reconstructed pixels of a first block of a picture. The storage device at least stores a portion of the reconstructed pixels of the first block, wherein a capacity of the storage device is smaller than a reconstructed data size of the picture. The intra prediction circuit performs intra prediction of a second block of the picture based at least partly on pixel data obtained from the storage device.