Abstract: A hardware functional module sends, to an aggregation module and in a standardized message format, first status information associated with the hardware functional module according to a first set of reporting rules via a first dedicated link. The firmware functional module sends, to the aggregation module and in the standardized message format, second status information associated with the firmware functional module according to a second set of reporting rules via a second dedicated link. The aggregation module aggregates the first status information in the standardized message format and the second status information in the standardized message format and inserts a timestamp to obtain a timestamped and aggregated message stream. The timestamped and aggregated message stream enables a visualization system to analyze the hardware functional module and the firmware functional module.

Abstract: A selection associated with a desired set of visual information, associated with a system on chip (SOC) that includes a hardware functional module and a firmware functional module, is received. A template is selected from a plurality of available templates based at least in part on the selection associated with the desired set of visual information. The selected template is used by the SOC to generate reported information, including by configuring the hardware functional module, as prescribed by the selected template, to generate select hardware-reported information and configuring the firmware functional module, as prescribed by the selected template, to generate select firmware-reported information. The reported information is received and the desired set of visual information is displayed.

Abstract: An interface receives reported information from a system on chip (SOC), where the reported information includes: (1) hardware-reported information that is reported by a hardware functional module included in the SOC and (2) firmware-reported information that is reported by a firmware functional module included in the SOC. A processor receives one or more display settings and generates visual information based at least in part on: (1) the one or more display settings, (2) the hardware-reported information, and (3) the firmware-reported information. The visual information is displayed via a display.

Abstract: A hardware functional module sends, to an aggregation module and in a standardized message format, first status information associated with the hardware functional module according to a first set of reporting rules via a first dedicated link. The firmware functional module sends, to the aggregation module and in the standardized message format, second status information associated with the firmware functional module according to a second set of reporting rules via a second dedicated link. The aggregation module aggregates the first status information in the standardized message format and the second status information in the standardized message format and inserts a timestamp to obtain a timestamped and aggregated message stream. The timestamped and aggregated message stream enables a visualization system to analyze the hardware functional module and the firmware functional module.

Abstract: For each data in a plurality of data, data is read from a cache unit. For each data in the plurality of data, a group to which the data read from the cache unit belongs to is determined based at least in part on a predetermined grouping rule. A determination is made of (1) a quantity of groups and (2) a quantity of data corresponding to each group after determining the groups to which the plurality of data belong. Data belonging to a same group is written into a contiguous storage space of the cache unit, including by: sequentially reading the plurality of data from the cache unit and sequentially writing the plurality of data into the cache unit.

Abstract: An interface receives reported information from a system on chip (SOC), where the reported information includes: (1) hardware-reported information that is reported by a hardware functional module included in the SOC and (2) firmware-reported information that is reported by a firmware functional module included in the SOC. A processor receives one or more display settings and generates visual information based at least in part on: (1) the one or more display settings, (2) the hardware-reported information, and (3) the firmware-reported information. The visual information is displayed via a display.

Abstract: A system on chip (SOC) system includes functional modules, including a first and second functional module. The first and second functional module are configured to send, to an aggregation module and in a standardized message format, first and second status information associated with the first and second functional module according to a first and second set of one or more reporting rules, respectively. The aggregation module aggregates the first status information in the standardized message format and the second status information in the standardized message format and insert a timestamp to obtain a timestamped and aggregated message stream. The timestamped and aggregated message stream is stored and enables a visualization system to analyze the first functional module and the second functional module.

Abstract: A system on chip (SOC) system includes functional modules, including a first and second functional module. The first and second functional module are configured to send, to an aggregation module and in a standardized message format, first and second status information associated with the first and second functional module according to a first and second set of one or more reporting rules, respectively. The aggregation module aggregates the first status information in the standardized message format and the second status information in the standardized message format and insert a timestamp to obtain a timestamped and aggregated message stream. The timestamped and aggregated message stream is stored and enables a visualization system to analyze the first functional module and the second functional module.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: Systems and method provide for consistent throughput of one or more compression engines. Data received from an input stream is stored in a buffer. Data is read from the buffer and distributed to the compression engines. Latency of the compression engines is monitored. If latency exceeds a threshold, data is read from the buffer and written to an output stream simultaneously with reading of data and inputting it to the compression engines. Data from the input stream may be evaluated for likely compressibility and non-compressible data may be written to the output stream bypassing both the buffer and the compression engines.

Abstract: Data words written to an SSD device, or other device or output data stream, may be randomized using a seed based on physical addressing information, such as a page address, column address, and a cycle count for the page address. This enables the storage and de-randomization of variable length data blocks stored at random locations within a page without requiring storage of additional data, which would make recovery impossible if lost in prior approaches. The page address, column address, and block address are physical attributes of the storage location for the data word and do not need to be saved and therefore will not be lost making recovery of the seed always possible. The cycle count can be saved and, if lost, limited trials with range of cycle counts can be exercised to de-randomize the data word and decoding may be used to determine whether descrambling was successful.

Abstract: Data words written to an SSD device, or other device or output data stream, may be randomized using a seed based on physical addressing information, such as a page address, column address, and a cycle count for the page address. This enables the storage and de-randomization of variable length data blocks stored at random locations within a page without requiring storage of additional data, which would make recovery impossible if lost in prior approaches. The page address, column address, and block address are physical attributes of the storage location for the data word and do not need to be saved and therefore will not be lost making recovery of the seed always possible. The cycle count can be saved and, if lost, limited trials with range of cycle counts can be exercised to de-randomize the data word and decoding may be used to determine whether descrambling was successful.

Abstract: Data words written to an SSD device, or other device or output data stream, may be randomized using a seed based on physical addressing information, such as a page address, column address, and a cycle count for the page address. This enables the storage and de-randomization of variable length data blocks stored at random locations within a page without requiring storage of additional data, which would make recovery impossible if lost in prior approaches. The page address, column address, and block address are physical attributes of the storage location for the data word and do not need to be saved and therefore will not be lost making recovery of the seed always possible. The cycle count can be saved and, if lost, limited trials with range of cycle counts can be exercised to de-randomize the data word and decoding may be used to determine whether descrambling was successful.

Abstract: Systems and method for reading compressed data from non-volatile storage such as an SSD device are disclosed. A logical section, e.g. page, of data includes a plurality of data blocks that are compressed such that the lengths thereof are different. A header section of the page stores headers for the data blocks and storing a length for each data block. The header section may be a codeword encoding the headers according to an error correction scheme. To read out a data block a hardware decoder requests reading of the page and transfers the header section into a hardware decoder that decodes the headers to obtain an offset for a desired data block. Without instructing reading of the page, the offset is used by the hardware decoder to request transfer of the desired data block that is then decoded and returned to a requesting device.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: An inspection method is provided herein. The inspection method is adapted for an inspection device. The inspection method includes: optically scanning an examining target for generating a scanned image; reconstructing the scanned image for a reconstructed volume; adjusting a slicing direction associated with the examining target for slicing the reconstructed volume into a sliced image; inspecting the sliced image for analyzing one or more features of the examining target; and outputting an inspection result of the examining target.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: An inspection method is provided herein. The inspection method is adapted for an inspection device. The inspection method includes: optically scanning an examining target for generating a scanned image; reconstructing the scanned image for a reconstructed volume; adjusting a slicing direction associated with the examining target for slicing the reconstructed volume into a sliced image; inspecting the sliced image for analyzing one or more features of the examining target; and outputting an inspection result of the examining target.