Abstract: A display assembly, a display device and a driving method for the display assembly are provided. The display assembly includes: a dimming array (10) and a pixel array (20) stacked together; wherein the dimming array (10) includes a plurality of dimming units (101) arranged in an array; the pixel array (20) includes a plurality of pixel units (201) arranged in an array; each dimming unit (101) corresponds to at least one pixel unit (201), and different dimming units (101) correspond to different pixel units (201), respectively. The display assembly further includes: a first driver chip (102) configured to drive the dimming array (10). The number of output channels of the first driver chip (102) is equal to the number of columns of dimming units (101) in the dimming array (10), and each output channel of the first driver chip (102) is connected to one column of dimming units (101).

Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, a gate driving circuit, power lines, a first signal line group, and a second signal line group. The gate driving circuit includes cascaded shift register units; the power lines are configured to provide power signals to the shift register units; the first signal line group includes at least one clock signal line, and the clock signal line is configured to provide a clock signal to the shift register units; the second signal line group includes a trigger signal line, and the trigger signal line is configured to provide a trigger signal to a first-stage shift register unit; and the gate driving circuit includes at least one transistor, and an extending direction of a channel of the transistor is parallel to an extending direction of the one clock signal line.

Abstract: A motor and a torque transducer box, an end cover front panel is installed at a front portion of the motor, the torque transducer box is installed at a front portion of the end cover front panel, a transmission pole is installed in the an extrusion rotating wheel, thermal dissipation and explosion proof boxes are installed on a surface of the motor, a sealing and thermal insulation module is installed at a front portion of the transmission pole, two sets of cable wrapping posts are symmetrically provided at the surface of the motor, and two sets of correction boxes are symmetrically provided at a surface of a rotor assembly.

Abstract: Disclosed herein includes a system, a method, and a device for improving power efficiency of a neural network implemented in an AI chip. In a neural network, large amounts of computations for multiply and accumulate can result in frequent toggles or transitions in states of logic circuits in the AI chip. Such frequent toggles or transitions of states of logic circuits can cause a large overall power consumption. In one aspect, to minimize the number of toggles, a sequence or order of computations can be rearranged. In one approach, total hamming distances for weights or input strings in different arrangements or sequences can be identified, and an arrangement or a sequence of weights or input strings with a reduced or minimum total hamming distance can be identified. An arrangement or a sequence of weights that render a reduced total hamming distance can be identified.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a first transistor, a second transistor and a storage capacitor. The display substrate further includes an extension portion protruding from the gate electrode of the first transistor, and the extension portion is extended from the gate electrode of the first transistor in the second direction; the extension portion is at least partially overlapped with the first electrode of the second transistor in a direction perpendicular to the base substrate and is electrically connected with the first electrode of the second transistor; in the first direction, the extension portion has a second side closest to the second capacitor electrode, and the second side is recessed in a direction away from the second capacitor electrode.

Abstract: A communication method and a communications apparatus, where the method may include: selecting or re-selecting, by a terminal device, from a first cell to a second cell through cell selection or re-selection, where radio access technologies of the first cell and the second cell are different, and where the terminal device is in an inactive mode in the first cell; re-selecting, by the terminal device, to the second cell through cell re-selection; and initiating, by the terminal device, a registration procedure after completing the cell re-selection. When the terminal device in inactive mode performs cell re-selection based on different radio technologies, the terminal device initiates the registration procedure or a service request procedure, for NAS signaling connection recovery. When the terminal device changes a radio access technology, a network device can update information.

Abstract: The present disclosure discloses an electroluminescent display panel and a display device. The electroluminescent display panel includes a plurality of repeat units, each of the plurality of repeat units includes a plurality of sub-pixels, and each of the plurality of sub-pixels includes: a first conductive layer, located on a substrate; a first insulation layer, located on the first conductive layer and including a first hole, in which the first hole exposes a portion of the first conductive layer; and an anode, located on the first insulation layer and including a main portion and an auxiliary portion which are electrically connected to each other. The auxiliary portion is electrically connected to the first conductive layer through the first hole. In at least one sub-pixel, an orthographic projection of the main portion on the substrate does not overlap an orthographic projection of the first hole on the substrate.

Abstract: The present disclosure provides a driving circuit, a driving method, a shift register and a display device. The drive circuit includes a first control circuit, a second control circuit, a first output circuit, a second output circuit and an output terminal; the first control circuit is configured to connect or disconnect the first node and the first control voltage terminal under the control of a control signal provided by the control terminal; the second control circuit is configured to connect or disconnect the second node and the second control voltage terminal under the control of the control signal.

Abstract: Provided is a display system, including one or more display screens (11, 12), a plurality of source drivers (13, 14), a timing controller (15) and a graphics processing unit (16). Each display screen (11, 12) is connected to one or more source drivers (13, 14). The graphic processing unit (16) is connected to the timing controller (15). The timing controller (15) is connected to the plurality of source drivers (13, 14). The graphic processing unit (16) is configured to determine each image of the one or more display screens (11, 12) and transmit the image to the timing controller (15). The timing controller (15) is configured to divide each image of the one or more display screens (11, 12) into a plurality of sub-images in a P2P transmission manner, and output in parallel the corresponding sub-images to the plurality of source drivers (13, 14).

Abstract: The present disclosure provides display substrate and display device, and belongs to the field of display technology. The display substrate of the disclosure has mounting region, first display region adjacent to mounting region, and second display region surrounding first display region and/or mounting region. The display substrate comprises: substrate; driving circuit layer on substrate and comprising pixel driving circuits in first display region and second display region, and arrangement density of pixel driving circuits in second display region is less than that of pixel driving circuits in second display region; and light emitting devices in mounting region, first display region, and second display region, first electrode of each light emitting device being electrically coupled to a corresponding pixel driving circuit, and pixel driving circuit electrically coupled to first electrode of light emitting device in the mounting region being located in first display region.

Abstract: The present disclosure provides a motherboard and a manufacturing method for the motherboard, the motherboard includes at least one display area, a periphery area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors and at least one thin film transistor. The plurality of test terminals are respectively electrically connected to the electrostatic discharge line through the plurality of resistors. At least one of the plurality of resistors includes an inorganic nonmetal trace. The at least one thin film transistor includes an active layer, and the inorganic nonmetal trace includes a same semiconductor matrix material as the active layer of the at least one thin film transistor.

Abstract: The present disclosure provides a display panel and an electronic device. The display panel includes: a base substrate; and a pixel arranged on the base substrate, wherein the pixel includes a first sub-pixel including a first sub-pixel drive circuit and a first light emitting element and a second sub-pixel including a second sub-pixel drive circuit and a second light emitting element, the first and second sub-pixel drive circuits are arranged sequentially in a first direction and extend in a second direction, wherein the first light emitting element includes a first anode, the second light emitting element includes a second anode, an orthographic projection of each of the first and the second anodes partially covers an orthographic projections of the first and second sub-pixel drive circuits, and the orthographic projection of the first anode does not overlap the orthographic projection of the second anode.

Abstract: The present disclosure relates to communication methods and apparatus. In one example method, a first message from a relay terminal is received by a first terminal. The first message includes first indication information, an application layer identifier of a second terminal, and a first address of the second terminal. The first indication information can indicate a first unicast link between the first terminal and the relay terminal. The first terminal updates first information of the first unicast link based on the first message to obtain updated second information of the first unicast link. The second information includes the application layer identifier of the second terminal and the first address.

Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, including a pixel array region and a peripheral region; and a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are in the peripheral region and located on a first side of the base substrate. The first scan driving circuit includes a plurality of cascaded first shift registers; the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit; the first signal line group includes at least one timing signal line; and the second signal line group is on a side of the plurality of power lines and the first signal line group away from the pixel array region.

Abstract: The present disclosure provides a display substrate, a display device, a mask plate, and a manufacturing method. The manufacturing method includes forming a pattern structure on a base substrate including a first substrate portion and a second substrate portion adjacent to the first substrate portion, wherein the pattern structure is formed on the first substrate portion; forming a planarization layer on the base substrate, which includes a first planarization layer on the first substrate portion and a second planarization layer on the second substrate portion, wherein a projection of the first planarization layer on the base substrate at least partially covers that of the pattern structure on the base substrate; and removing a part of the first planarization layer to reduce a difference between a height of a surface of the first planarization layer and a height of a surface of the second planarization layer.

Abstract: A method, non-transitory computer readable medium and an evaluation system for evaluating an intermediate product related to a three dimensional NAND memory unit. The evaluation system may include an imager and a processing circuit. The imager may be configured to obtain, via an open gap, an electron image of a portion of a structural element that belongs to an intermediate product. The structural element may include a sequence of layers that include a top layer that is followed by alternating nonconductive layers and recessed conductive layers. The imager may include electron optics configured to scan the portion of the structural element with an electron beam that is oblique to a longitudinal axis of the open gap. The processing circuit is configured to evaluate the intermediate product based on the electron image. The open gap (a) exhibits a high aspect ratio, (b) has a width of nanometric scale, and (c) is formed between structural elements of the intermediate product.

Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels which are arranged in a sub-pixel array in a first direction and a second direction. At least one sub-pixel includes a first transistor, a second transistor, a third transistor, and a storage capacitor. An active layer of the third transistor includes a body region and a first via hole region successively arranged in the first direction and electrically connected with each other; a first electrode of the third transistor is electrically connected to the first via hole region through a first via hole which is shifted in the second direction with respect to the body region, allowing the active layer incudes a first active layer side connecting the body region and the first via hole region; an extension direction of the first active layer side intersects with both the first direction and the second direction.

Abstract: The invention discloses an intelligent plugging robot and method thereof for rerouting, maintaining and repairing long-distance pipelines. The intelligent plugging robot includes a through-flow governor, a flow-blocking mechanism and a telescopic mechanism, wherein the through-flow governor and the flow-blocking mechanism are symmetrically distributed on both sides of the device. The invention can realize remote, fast, safe and accurate plugging during maintaining and repairing the long-distance pipeline, wherein the telescopic mechanism cooperates with the flow-blocking mechanism to move autonomously in the pipe to achieve precise positioning, the through-flow governor can not only adjust the plugging robot but also ensure the cleaning of the pipe wall, make it stable contact with the signal transceiver, and realize the stable communication between the robot in the pipe and the remote monitoring machine.

Abstract: This application provides a communication method and apparatus, to resolve a problem that a PDU session of a terminal in an inactive mode fails to be activated. The method performed by a first core network device includes: sending first downlink information to a first RAN node, where the first downlink information is used by the first RAN node to activate a PDU session of a terminal, and the PDU session is in an inactive state; receiving indication information from the first RAN node, where the indication information indicates that the PDU session fails to be activated; and sending second downlink information to a second RAN node based on the indication information, where the second downlink information is used by the second RAN node to activate the PDU session of the terminal. This application relates to the field of communications technologies.

Abstract: The present disclosure relates to the field of display technologies, and provides an array substrate, a manufacturing method thereof, and a display panel.