Abstract: A configurable generic filter hardware block and corresponding methods are provided. A configurable generic filter hardware block includes a plurality of multipliers; a plurality of adders; and one or more multiplexers. The, configurable generic filter hardware block is configured using a header data structure, and the header data structure includes a pointer to a memory location storing a plurality of input samples, a pointer to a memory location storing a plurality of output samples and a coefficient selection control value. The configurable generic filter hardware block is optionally invoked by a convolution instruction in one or more of a vector processor and a state machine. An exemplary Generic Filter Iteration loads input samples; selects coefficients; convolves the input samples and the selected coefficients and stores output samples. The header data structures are optionally stored sequentially in memory and processed in a single loop.

Abstract: A configurable transmitter hardware block and corresponding methods for configuring and employing the configurable transmitter hardware block are provided. A configurable transmitter that supports a plurality of channel types comprises a bit selection/manipulation module that performs a bit selection function and/or a bit manipulation function; a modulation mapping module, a gain multiplication module; a spreading/scrambling module that performs a spreading function and/or a scrambling function; and a channel combining module, wherein the configurable transmitter is configured using a plurality of sets of control signals that configure one or more of the modules, wherein each of the sets of control signals are precomputed for a corresponding one of the channel types.

Abstract: A configurable generic filter hardware block and corresponding methods are provided. A configurable generic filter hardware block comprises a plurality of multipliers; a plurality of adders; and one or more multiplexers, wherein the configurable generic filter hardware block is configured using a header data structure, the header data structure comprises a pointer to a memory location storing a plurality of input samples, a pointer to a memory location storing a plurality of output samples and a coefficient selection control value. The configurable generic filter hardware block is optionally invoked by a convolution instruction in one or more of a vector processor and a state machine. An exemplary Generic Filter Iteration comprises loading input samples; selecting coefficients; convolving the input samples and the selected coefficients and storing output samples. Each Generic Filter Iteration has a corresponding header data structure.