Patents by Inventor Meng-Lin Yu

Meng-Lin Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10430663
    Abstract: An image annotation method includes the following. Image frames are acquired. One or more target objects are identified and tracked from the image frames. Candidate key image frames are selected from the frames according to a first selection condition. First similarity indexes of the candidate key image frames are determined. Second similarity indexes of a plurality of adjacent frames are determined. The candidate key image frames as well as the adjacent frames that meet a second selection condition are selected as key image frames. The key image frames are displayed on a graphical user interface. Annotation information about the one or more target objects is display through the graphical user interface.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: October 1, 2019
    Assignee: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Hsin-Han Chiang, Yen-Lin Chen, Chien Lin, Chao-Wei Yu, Meng-Tsan Li
  • Publication number: 20190156123
    Abstract: An image annotation method includes the following. Image frames are acquired. One or more target objects are identified and tracked from the image frames. Candidate key image frames are selected from the frames according to a first selection condition. First similarity indexes of the candidate key image frames are determined. Second similarity indexes of a plurality of adjacent frames are determined. The candidate key image frames as well as the adjacent frames that meet a second selection condition are selected as key image frames. The key image frames are displayed on a graphical user interface. Annotation information about the one or more target objects is display through the graphical user interface.
    Type: Application
    Filed: December 7, 2017
    Publication date: May 23, 2019
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Hsin-Han CHIANG, Yen-Lin CHEN, Chien LIN, Chao-Wei YU, Meng-Tsan LI
  • Publication number: 20190146768
    Abstract: A vehicle radar setting method includes the step of providing a setting tool, the step pf using the setting tool to choose vehicle year, brand and model, the step of fetching the corresponding vehicle radar main program according to the chosen vehicle year brand and model, the step of transmitting the vehicle radar main program to the vehicle radar, and the step of enabling the vehicle radar to receive and install the vehicle radar main program.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 16, 2019
    Inventors: San-Chuan YU, Yu-Tao YU, Meng-Yu HO, Jyong LIN
  • Publication number: 20180164924
    Abstract: There is provided a capacitive touch device including a touch panel, a detection circuit and a processing unit. The touch panel includes a plurality of drive electrodes and a plurality of receiving electrodes configured to form a coupling electric field with an external touch panel, and the receiving electrodes are respectively configured to output a detection signal. The detection circuit is coupled to one of the receiving electrodes and configured to modulate the detection signal with two signals to generate two detection components. The processing unit is configured to obtain a phase value according to the two detection components to accordingly decode transmission data.
    Type: Application
    Filed: February 9, 2018
    Publication date: June 14, 2018
    Inventors: Sung-Han WU, Yu-Han CHEN, Ming-Hung TSAI, Meng-Lin YU, Hsin-Chia CHEN
  • Patent number: 9952732
    Abstract: There is provided a capacitive touch device including a touch panel, a detection circuit and a processing unit. The touch panel includes a plurality of drive electrodes and a plurality of receiving electrodes configured to form a coupling electric field with an external touch panel, and the receiving electrodes are respectively configured to output a detection signal. The detection circuit is coupled to one of the receiving electrodes and configured to modulate the detection signal with two signals to generate two detection components. The processing unit is configured to obtain a phase value according to the two detection components to accordingly decode transmission data.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: April 24, 2018
    Assignee: PIXART IMAGING INC.
    Inventors: Sung-Han Wu, Yu-Han Chen, Ming-Hung Tsai, Meng-Lin Yu, Hsin-Chia Chen
  • Patent number: 9778902
    Abstract: Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: October 3, 2017
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Chengzhou Li, Albert Molina, Joseph H. Othmer, Steven C. Pinault, Meng-Lin Yu, Joseph Williams, Ramon Sanchez Perez, Jian-Guo Chen
  • Patent number: 9612794
    Abstract: Software implementations are provided for performing IQ imbalance correction and/or RF equalization. An input signal, x, is processed in software by executing a vector convolution instruction to apply the input signal, x, to a first complex FIR filter that performs one or more of RF equalization and IQ imbalance correction; and executing a vector convolution instruction to apply a conjugate x* of the input signal, x, to a second complex FIR filter that performs the one or more of RF equalization and IQ imbalance correction, wherein the second complex FIR filter is in parallel with the first complex FIR filter. The first and second complex FIR filters have complex coefficients and the input signal comprises a complex signal.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Joseph H. Othmer, Meng-Lin Yu
  • Patent number: 9529567
    Abstract: A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to ?; and computing a fine corrective value using a polynomial approximation.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Albert Molina, Joseph H. Othmer, Parakalan Venkataraghavan, Meng-Lin Yu, Joseph Williams
  • Publication number: 20160282996
    Abstract: There is provided a capacitive touch device including a touch panel, a detection circuit and a processing unit. The touch panel includes a plurality of drive electrodes and a plurality of receiving electrodes configured to form a coupling electric field with an external touch panel, and the receiving electrodes are respectively configured to output a detection signal. The detection circuit is coupled to one of the receiving electrodes and configured to modulate the detection signal with two signals to generate two detection components. The processing unit is configured to obtain a phase value according to the two detection components to accordingly decode transmission data.
    Type: Application
    Filed: June 8, 2016
    Publication date: September 29, 2016
    Inventors: Sung-Han WU, Yu-Han CHEN, Ming-Hung TSAI, Meng-Lin YU, Hsin-Chia CHEN
  • Patent number: 9363068
    Abstract: A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: June 7, 2016
    Assignee: INTEL CORPORATION
    Inventors: Kameran Azadet, Joseph Williams, Meng-Lin Yu
  • Patent number: 9362977
    Abstract: In one embodiment, the present invention is a method for performing incremental preamble detection in a wireless communication network. The method processes non-overlapping chunks of incoming antenna data, where each chunk is smaller than the preamble length, to detect the signature of the transmitted preamble. For each chunk processed, chips of the chunk are correlated with possible signatures employed by the wireless network to update a set of correlation profiles, each profile comprising a plurality of profile values. Further, an intermediate detection is performed by comparing the updated profile values to an intermediate threshold that is also updated for each chunk. Upon receiving the final chunk, the correlation profiles are updated, and a final preamble detection is made by comparing the updated profile values to a final threshold. Detections are performed on an incremental basis to meet latency requirements of the wireless network.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: June 7, 2016
    Assignee: Intel Corporation
    Inventors: Ivan Leonidovich Mazurenko, Alexander Alexandrovich Petyushko, Meng-Lin Yu, Jian-Guo Chen
  • Patent number: 9280315
    Abstract: A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises N1 samples; and performing a weighted sum of the time shifted versions of the vector by a vector of N1 coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 8, 2016
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Meng-Lin Yu, Joseph Othmer, Joseph Williams, Albert Molina
  • Patent number: 9184787
    Abstract: In one embodiment, a programmable vector processor performs preamble detection in a wireless communication network. Implementation of preamble detection in the vector processor is made possible by a set of vector instructions that include (i) a circular load instruction for loading vectors of received data, (ii) a correlation instruction for correlating the vectors of received data with vectors of the scrambling code to concurrently generate a plurality of complex correlations, (iii) a partial-transpose instruction for arranging vectors of the complex correlations for use by a Fast Hadamard Transform (FHT) processor, and (iv) an FHT instruction for performing FHT processing on a vector of complex correlations. Implementing preamble detection in the vector processor allows more of the received data to be processed concurrently. As a result, preamble detectors of the disclosure may detect preambles using fewer clock cycles than that of comparable preamble detectors implemented using hardware accelerators.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 10, 2015
    Assignee: Intel Corporation
    Inventors: Meng-Lin Yu, Jian-Guo Chen, Alexander Alexandrovich Petyushko, Ivan Leonidovich Mazurenko
  • Patent number: 9100228
    Abstract: A method and system for canonical channel estimation in the Long Term Evolution uplink where a multi-frequency signal is generated and then converted to frequency spectrum which is then convolved in the frequency domain with a truncated window function to obtain a time domain channel impulse response. The time domain channel impulse response can be then transformed to a frequency domain to produce a down sampled user channel response, which can be then linearly interpolated to provide a channel estimate for a plurality of subcarriers. Such an approach achieves channel estimation within Long Term Evolution at only canonical locations to reduce complexity without loss in channel entropy.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: August 4, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Samer Hijazi, Kameran Azadet, Meng-Lin Yu, Joseph Othmer, Ramon Sanchez Perez
  • Patent number: 8982992
    Abstract: Block-based crest factor reduction (CFR) techniques are provided. An exemplary block-based crest factor reduction method comprises obtaining a block of data samples comprised of a plurality of samples; applying the block of data to a crest factor reduction block; and providing a processed block of data from the crest factor reduction block. The block-based crest factor reduction method can optionally be iteratively performed a plurality of times for the block of data. The block of data samples can comprise an expanded block having at least one cursor block. For example, at least two pre-cursor blocks and one post-cursor block can be employed. The peaks can be cancelled, for example, only in the block of data samples and in a first of the pre-cursor blocks.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 17, 2015
    Assignee: LSI Corporation
    Inventors: Kameran Azadet, Albert Molina, Joseph H. Othmer, Meng-Lin Yu, Ramon Sanchez Perez
  • Publication number: 20140317163
    Abstract: A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function.
    Type: Application
    Filed: January 30, 2014
    Publication date: October 23, 2014
    Applicant: LSI Corporation
    Inventors: Kameran Azadet, Joseph Williams, Meng-Lin Yu
  • Patent number: 8842665
    Abstract: A method of applying an order N fast Hadamard transform (FHT) of a vector U using a mixed radix FHT in a receiver of a communication system, the N a positive integer, when receiving signals from a transmitter over a channel and generating the vector U. The method includes, in an FHT module of a decoder in the receiver, planning n stages of the mixed radix FHT, where the n is a positive integer, each stage defined by corresponding logic, decomposing the order N FHT into n low order FHTs, such that N=KnKn?1 . . . K1 and U=UKnKn?1 . . . K1, where the K is a positive integer, calculating, via the corresponding logic, each low order FHT at each stage, wherein input vectors of a subsequent stage are calculated in a proceeding stage, and reconstructing, by the decoder, calculated results of the each low order FHT to form an output vector output the decoder.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: September 23, 2014
    Assignee: LSI Corporation
    Inventors: Chengzhou Li, Meng-Lin Yu
  • Patent number: 8804672
    Abstract: In one embodiment, the invention is a method for performing preamble detection in a wireless communication network. The method performs a first dwell, wherein non-overlapping chunks of received data are processed to generate partial correlation values for each possible combination of a signature code and delay. Candidate selection is performed by comparing each of the partial correlation values to a candidate-selection threshold. For each detected candidate, the chunks of received data are processed to generate full correlation values. Each full correlation value is then compared to a preamble-detection threshold to detect a transmitted signature. Generating full correlation values for only the selected candidates reduces the computation complexity over prior-art methods that generate full correlation values for all signatures at all delays.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: August 12, 2014
    Assignee: LSI Corporation
    Inventors: Ivan L. Mazurenko, Alexander A. Petyushko, Meng-Lin Yu, Jian-Guo Chen
  • Patent number: 8719323
    Abstract: A method for efficient state transition matrix based LFSR computations are disclosed. A polynomial associated with a linear feedback shift register is defined. This polynomial is used to generate a single step state transition matrix. The single step state transition matrix is then modified into a more general k-step state transition matrix. The resultant combined matrix is reduced in size and can be multiplied by a state input vector, ultimately producing a plurality of next state-input vectors thereby providing improved efficiency in computing a LFSR.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: May 6, 2014
    Assignee: LSI Corporation
    Inventor: Meng-Lin Yu
  • Publication number: 20140108477
    Abstract: A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises Ni samples; and performing a weighted sum of the time shifted versions of the vector by a vector of Ni coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.
    Type: Application
    Filed: October 26, 2012
    Publication date: April 17, 2014
    Applicant: LSI Corporation
    Inventors: Kameran Azadet, Meng-Lin Yu, Joseph H. Othmer, Joseph Williams, Albert Molina