Abstract: A spatial positioning method is provided. The method includes steps of: dividing an activity space into a plurality of activity regions; selecting a plurality of positions in the activity space or within a distance range of the activity space as a plurality of base station candidate positions; predicting connection states between the plurality of base stations that are disposed respectively at the plurality of station candidate positions and a mobile robot moving to each of the plurality of activity regions; selecting some of the base station candidate positions as a plurality of base station positions according to the connection states; disposing the plurality of base stations respectively at the plurality of base station positions; and wirelessly connecting the mobile robot respectively moving to the plurality of activity regions to some of the plurality of base stations to position the mobile robot.

Abstract: Systems, methods, and apparatuses relating to a user defined formatting instruction to configure multicast Benes network circuitry are described.

Abstract: Systems, methods, and apparatuses relating to a user defined formatting instruction to configure multicast Benes network circuitry are described.

Abstract: There is provided a parallel sensing touch control device including a capacitive sensor array processed by differential unit. In one detection interval, the device is concurrently conducting more than one sensing electrode of the capacitive sensor array so as to reduce a scanning interval of the capacitive sensor array. The differential unit performs a differential operation on detected signals to cancel out common mode noise.

Abstract: There is provided a parallel sensing touch control device including a capacitive sensor array processed by differential unit. In one detection interval, the device is concurrently conducting more than one sensing electrode of the capacitive sensor array so as to reduce a scanning interval of the capacitive sensor array. The differential unit performs a differential operation on detected signals to cancel out common mode noise.

Abstract: There is provided a capacitive touch device including a touch panel, a detection circuit and a processing unit. The touch panel includes a plurality of drive electrodes and a plurality of receiving electrodes configured to form a coupling electric field with an external touch panel, and the receiving electrodes are respectively configured to output a detection signal. The detection circuit is coupled to one of the receiving electrodes and configured to modulate the detection signal with two signals to generate two detection components. The processing unit is configured to obtain a phase value according to the two detection components to accordingly decode transmission data.

Abstract: There is provided a capacitive touch device including a touch panel, a detection circuit and a processing unit. The touch panel includes a plurality of drive electrodes and a plurality of receiving electrodes configured to form a coupling electric field with an external touch panel, and the receiving electrodes are respectively configured to output a detection signal. The detection circuit is coupled to one of the receiving electrodes and configured to modulate the detection signal with two signals to generate two detection components. The processing unit is configured to obtain a phase value according to the two detection components to accordingly decode transmission data.

Abstract: There is provided a capacitive touch device including a touch panel, a detection circuit and a processing unit. The touch panel includes a plurality of drive electrodes and a plurality of receiving electrodes configured to form a coupling electric field with an external touch panel, and the receiving electrodes are respectively configured to output a detection signal. The detection circuit is coupled to one of the receiving electrodes and configured to modulate the detection signal with two signals to generate two detection components. The processing unit is configured to obtain a phase value according to the two detection components to accordingly decode transmission data.

Abstract: Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.

Abstract: Software implementations are provided for performing IQ imbalance correction and/or RF equalization. An input signal, x, is processed in software by executing a vector convolution instruction to apply the input signal, x, to a first complex FIR filter that performs one or more of RF equalization and IQ imbalance correction; and executing a vector convolution instruction to apply a conjugate x* of the input signal, x, to a second complex FIR filter that performs the one or more of RF equalization and IQ imbalance correction, wherein the second complex FIR filter is in parallel with the first complex FIR filter. The first and second complex FIR filters have complex coefficients and the input signal comprises a complex signal.

Abstract: A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to ?; and computing a fine corrective value using a polynomial approximation.

Abstract: There is provided a capacitive touch device including a touch panel, a detection circuit and a processing unit. The touch panel includes a plurality of drive electrodes and a plurality of receiving electrodes configured to form a coupling electric field with an external touch panel, and the receiving electrodes are respectively configured to output a detection signal. The detection circuit is coupled to one of the receiving electrodes and configured to modulate the detection signal with two signals to generate two detection components. The processing unit is configured to obtain a phase value according to the two detection components to accordingly decode transmission data.

Abstract: A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function.

Abstract: In one embodiment, the present invention is a method for performing incremental preamble detection in a wireless communication network. The method processes non-overlapping chunks of incoming antenna data, where each chunk is smaller than the preamble length, to detect the signature of the transmitted preamble. For each chunk processed, chips of the chunk are correlated with possible signatures employed by the wireless network to update a set of correlation profiles, each profile comprising a plurality of profile values. Further, an intermediate detection is performed by comparing the updated profile values to an intermediate threshold that is also updated for each chunk. Upon receiving the final chunk, the correlation profiles are updated, and a final preamble detection is made by comparing the updated profile values to a final threshold. Detections are performed on an incremental basis to meet latency requirements of the wireless network.

Abstract: A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises N1 samples; and performing a weighted sum of the time shifted versions of the vector by a vector of N1 coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.

Abstract: In one embodiment, a programmable vector processor performs preamble detection in a wireless communication network. Implementation of preamble detection in the vector processor is made possible by a set of vector instructions that include (i) a circular load instruction for loading vectors of received data, (ii) a correlation instruction for correlating the vectors of received data with vectors of the scrambling code to concurrently generate a plurality of complex correlations, (iii) a partial-transpose instruction for arranging vectors of the complex correlations for use by a Fast Hadamard Transform (FHT) processor, and (iv) an FHT instruction for performing FHT processing on a vector of complex correlations. Implementing preamble detection in the vector processor allows more of the received data to be processed concurrently. As a result, preamble detectors of the disclosure may detect preambles using fewer clock cycles than that of comparable preamble detectors implemented using hardware accelerators.

Abstract: A method and system for canonical channel estimation in the Long Term Evolution uplink where a multi-frequency signal is generated and then converted to frequency spectrum which is then convolved in the frequency domain with a truncated window function to obtain a time domain channel impulse response. The time domain channel impulse response can be then transformed to a frequency domain to produce a down sampled user channel response, which can be then linearly interpolated to provide a channel estimate for a plurality of subcarriers. Such an approach achieves channel estimation within Long Term Evolution at only canonical locations to reduce complexity without loss in channel entropy.

Abstract: Block-based crest factor reduction (CFR) techniques are provided. An exemplary block-based crest factor reduction method comprises obtaining a block of data samples comprised of a plurality of samples; applying the block of data to a crest factor reduction block; and providing a processed block of data from the crest factor reduction block. The block-based crest factor reduction method can optionally be iteratively performed a plurality of times for the block of data. The block of data samples can comprise an expanded block having at least one cursor block. For example, at least two pre-cursor blocks and one post-cursor block can be employed. The peaks can be cancelled, for example, only in the block of data samples and in a first of the pre-cursor blocks.

Abstract: A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function.

Abstract: A method of applying an order N fast Hadamard transform (FHT) of a vector U using a mixed radix FHT in a receiver of a communication system, the N a positive integer, when receiving signals from a transmitter over a channel and generating the vector U. The method includes, in an FHT module of a decoder in the receiver, planning n stages of the mixed radix FHT, where the n is a positive integer, each stage defined by corresponding logic, decomposing the order N FHT into n low order FHTs, such that N=KnKn?1 . . . K1 and U=UKnKn?1 . . . K1, where the K is a positive integer, calculating, via the corresponding logic, each low order FHT at each stage, wherein input vectors of a subsequent stage are calculated in a proceeding stage, and reconstructing, by the decoder, calculated results of the each low order FHT to form an output vector output the decoder.