Patents by Inventor Meng Meng Vanessa CHONG

Meng Meng Vanessa CHONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RELIABLE PASSIVATION LAYERS FOR SEMICONDUCTOR DEVICES
    Publication number: 20160181197
    Abstract: Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided. The top metal level includes top level conductive lines. A top dielectric layer which includes top via openings in communication with the top level conductive lines is formed over the top metal level. A patterned top conductive layer is formed on the top dielectric layer. The patterned top conductive layer includes a top via in the top via opening and a top conductive line. A first passivation sub-layer is formed to line the patterned conductive layer and exposed top dielectric layer. A plasma treatment is performed on the surface of the first passivation sub-layer to form a nitrided layer. A second passivation sub-layer is formed to line the nitrided layer. The plasma treatment improves the passivation integrity of the passivation stack.
    Type: Application
    Filed: February 29, 2016
    Publication date: June 23, 2016
    Inventors: Xuesong RAO, Meng Meng Vanessa CHONG, Chim Seng SEET, Hendro MARIO, Aison JOHN GEORGE, Chor Shu CHENG
  • Reliable passivation layers for semiconductor devices
    Patent number: 9293388
    Abstract: Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided. The top metal level includes top level conductive lines. A top dielectric layer which includes top via openings in communication with the top level conductive lines is formed over the top metal level. A patterned top conductive layer is formed on the top dielectric layer. The patterned top conductive layer includes a top via in the top via opening and a top conductive line. A first passivation sub-layer is formed to line the patterned conductive layer and exposed top dielectric layer. A plasma treatment is performed on the surface of the first passivation sub-layer to form a nitrided layer. A second passivation sub-layer is formed to line the nitrided layer. The plasma treatment improves the passivation integrity of the passivation stack.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xuesong Rao, Meng Meng Vanessa Chong, Chim Seng Seet, Hendro Mario, Aison John George, Chor Shu Cheng
  • RELIABLE PASSIVATION LAYERS FOR SEMICONDUCTOR DEVICES
    Publication number: 20150108654
    Abstract: Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided. The top metal level includes top level conductive lines. A top dielectric layer which includes top via openings in communication with the top level conductive lines is formed over the top metal level. A patterned top conductive layer is formed on the top dielectric layer. The patterned top conductive layer includes a top via in the top via opening and a top conductive line. A first passivation sub-layer is formed to line the patterned conductive layer and exposed top dielectric layer. A plasma treatment is performed on the surface of the first passivation sub-layer to form a nitrided layer. A second passivation sub-layer is formed to line the nitrided layer. The plasma treatment improves the passivation integrity of the passivation stack.
    Type: Application
    Filed: October 22, 2013
    Publication date: April 23, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xuesong RAO, Meng Meng Vanessa CHONG, Chim Seng SEET, Hendro MARIO, Aison JOHN GEORGE, Chor Shu CHENG