Patents by Inventor Meng Miao
Meng Miao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240140934Abstract: The technical field of pharmaceuticals. Disclosed are a triazole derivative, a method for preparing same, and use thereof. The triazole derivative has a structure as shown in formula I, and the triazole derivative of the present invention can be used as a CRM1 inhibitor for preparing a medicament for treating a disease related to CRM1 activity.Type: ApplicationFiled: March 11, 2022Publication date: May 2, 2024Applicant: SHENZHEN JIKANG PHARMACEUTICAL TECHNOLOGY CO., LTD.Inventors: Yongqiang ZHU, Meng LEI, Hang MIAO, Xueyuan WANG
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Patent number: 11955472Abstract: Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P? closer to insulator layer).Type: GrantFiled: December 17, 2021Date of Patent: April 9, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Meng Miao, Alain Loiseau, Souvick Mitra, Wei Liang, Robert J. Gauthier, Jr., Anindya Nath
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Publication number: 20240094468Abstract: Various embodiments disclosed herein describe photonic passive delay lines that have a waveguide wound into a plurality of straight segments and bends. The photonic passive delay lines are configured to reduce losses from parasitic modes of light generated at the bends. Embodiments of the photonic passive delay lines vary the dimensions of the straight segments to provide different amounts of dephasing between a mode of input light received by the photonic passive delay line and one or more parasitic modes.Type: ApplicationFiled: August 16, 2023Publication date: March 21, 2024Inventors: Jason S. Pelc, Yu Miao, Mark A. Arbore, Meng Huang, Zhechao Wang
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Publication number: 20230420448Abstract: A structure includes trigger control circuitry for an SCR including: a first transistor having two P-type semiconductor terminals connected to an Nwell and a Pwell of the SCR; a second transistor having two N-type semiconductor terminals connected to the Pwell and ground; and, optionally, an additional transistor having two P-type semiconductor terminals connected to the Nwell and ground. Control terminals of the transistors receive the same control signal (e.g., RST from a power-on-reset). When a circuit connected to the SCR for ESD protection is powered on, ESD risk is limited so RST switches to high. Thus, the first transistor and optional additional transistor turn off and the second transistor turns on, reducing leakage. When the circuit is powered down, the ESD risk increases so RST switches to low. Thus, the first transistor and optional additional transistor turn on and the second transistor turns off, lowering the trigger voltage and current.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Inventors: Souvick Mitra, Alain F. Loiseau, Robert J. Gauthier, JR., Meng Miao, Anindya Nath, Wei Liang
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Publication number: 20230420447Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.Type: ApplicationFiled: September 7, 2023Publication date: December 28, 2023Inventors: Robert J. GAUTHIER, JR., Meng MIAO, Alain F. LOISEAU, Souvick MITRA, You LI, Wei LIANG
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Patent number: 11804481Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.Type: GrantFiled: February 25, 2021Date of Patent: October 31, 2023Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Robert J. Gauthier, Jr., Meng Miao, Alain F. Loiseau, Souvick Mitra, You Li, Wei Liang
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Publication number: 20230197707Abstract: Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P- closer to insulator layer).Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Applicant: GlobalFoundries U.S. Inc.Inventors: Meng Miao, Alain Loiseau, Souvick Mitra, Wei Liang, Robert J. Gauthier, JR., Anindya Nath
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Patent number: 11631759Abstract: An ESD protection device may be provided, including: a substrate including a first conductivity region and a second conductivity region arranged therein. The first conductivity region may include a first terminal region and a second terminal region electrically coupled with each other. The second conductivity region may include a third terminal region and a fourth terminal region electrically coupled with each other. The second conductivity region may further include a fifth terminal region electrically coupled with the first and second terminal regions. The fifth terminal region may be arranged laterally between the third terminal region and the fourth terminal region. The first conductivity region, the first terminal region, the third terminal region, and the fifth terminal region may have a first conductivity type. The second conductivity region, the second terminal region, and the fourth terminal region may have a second conductivity type different from the first conductivity type.Type: GrantFiled: February 2, 2021Date of Patent: April 18, 2023Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Meng Miao, Alain François Loiseau, Souvick Mitra, Robert John Gauthier, Jr., You Li, Wei Liang
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Publication number: 20220320073Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a triple well structure within a semiconductor substrate. A base region is within a doped well of the triple well structure, a collector terminal is within the doped well and laterally separated from the base region by a first insulator and a first avalanche junction is defined between a first pair of oppositely-doped semiconductor regions within the collector terminal. An emitter terminal is within the third doped well of the triple well structure and laterally separated from the collector terminal by a second insulator. A second avalanche junction is defined between a second pair of oppositely-doped semiconductor regions of the emitter terminal.Type: ApplicationFiled: June 24, 2022Publication date: October 6, 2022Inventors: Robert J. Gauthier, JR., Alain F. Loiseau, Souvick Mitra, Tsung-Che Tsai, Meng Miao, You Li
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Patent number: 11444076Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a doped well in a semiconductor substrate, in addition to a base region, emitter region, and collector region in the doped well. An insulative material is within the doped well, with a first end horizontally adjacent the collector region and a second end opposite the first end. A doped semiconductor region is within the doped well adjacent the second end of the insulative material. The doped semiconductor region is positioned to define an avalanche junction between the collector region and the doped semiconductor region across the doped well.Type: GrantFiled: August 3, 2020Date of Patent: September 13, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Robert J. Gauthier, Jr., Alain F. Loiseau, Souvick Mitra, Tsung-Che Tsai, Meng Miao, You Li
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Publication number: 20220271028Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.Type: ApplicationFiled: February 25, 2021Publication date: August 25, 2022Inventors: Robert J. GAUTHIER, JR., Meng MIAO, Alain F. LOISEAU, Souvick MITRA, You LI, Wei LIANG
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Publication number: 20220246749Abstract: An ESD protection device may be provided, including: a substrate including a first conductivity region and a second conductivity region arranged therein. The first conductivity region may include a first terminal region and a second terminal region electrically coupled with each other. The second conductivity region may include a third terminal region and a fourth terminal region electrically coupled with each other. The second conductivity region may further include a fifth terminal region electrically coupled with the first and second terminal regions. The fifth terminal region may be arranged laterally between the third terminal region and the fourth terminal region. The first conductivity region, the first terminal region, the third terminal region, and the fifth terminal region may have a first conductivity type. The second conductivity region, the second terminal region, and the fourth terminal region may have a second conductivity type different from the first conductivity type.Type: ApplicationFiled: February 2, 2021Publication date: August 4, 2022Inventors: Meng MIAO, Alain François LOISEAU, Souvick MITRA, Robert John GAUTHIER JR., You LI, Wei LIANG
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Patent number: 11349304Abstract: Embodiments of the disclosure provide a circuit structure and method to control electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit. Circuit structures according to the disclosure may include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to part of the RC circuit. A mirror transistor coupled in parallel with the RC circuit transmits a current that is less than a current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode/cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device, derived from current in the mirror transistor, controls an anode/cathode current flow in the snapback device.Type: GrantFiled: October 28, 2020Date of Patent: May 31, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Alain F. Loiseau, Robert J. Gauthier, Jr., Souvick Mitra, You Li, Meng Miao, Wei Liang
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Publication number: 20220131369Abstract: Embodiments of the disclosure provide a circuit structure and method to control electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit. Circuit structures according to the disclosure may include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to part of the RC circuit. A mirror transistor coupled in parallel with the RC circuit transmits a current that is less than a current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode/cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device, derived from current in the mirror transistor, controls an anode/cathode current flow in the snapback device.Type: ApplicationFiled: October 28, 2020Publication date: April 28, 2022Inventors: Alain F. Loiseau, Robert J. Gauthier, JR., Souvick Mitra, You Li, Meng Miao, Wei Liang
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Patent number: 11289471Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge (ESD) device and methods of manufacture. The structure (ESD device) includes: a trigger collector region having fin structures of a first dopant type, a collector region having fin structures in a well of a second dopant type and further including a lateral ballasting resistance; an emitter region having a well of the second dopant type and fin structures of the first dopant type; and a base region having a well and fin structures of the second dopant type.Type: GrantFiled: August 24, 2020Date of Patent: March 29, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: You Li, Alain F. Loiseau, Souvick Mitra, Tsung-Che Tsai, Robert J. Gauthier, Jr., Meng Miao
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Publication number: 20220059523Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge (ESD) device and methods of manufacture. The structure (ESD device) includes: a trigger collector region having fin structures of a first dopant type, a collector region having fin structures in a well of a second dopant type and further including a lateral ballasting resistance; an emitter region having a well of the second dopant type and fin structures of the first dopant type; and a base region having a well and fin structures of the second dopant type.Type: ApplicationFiled: August 24, 2020Publication date: February 24, 2022Inventors: You LI, Alain F. LOISEAU, Souvick MITRA, Tsung-Che TSAI, Robert J. GAUTHIER, JR., Meng MIAO
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Publication number: 20220037309Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a doped well in a semiconductor substrate, in addition to a base region, emitter region, and collector region in the doped well. An insulative material is within the doped well, with a first end horizontally adjacent the collector region and a second end opposite the first end. A doped semiconductor region is within the doped well adjacent the second end of the insulative material. The doped semiconductor region is positioned to define an avalanche junction between the collector region and the doped semiconductor region across the doped well.Type: ApplicationFiled: August 3, 2020Publication date: February 3, 2022Inventors: Robert J. Gauthier, JR., Alain F. Loiseau, Souvick Mitra, Tsung-Che Tsai, Meng Miao, You Li
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Patent number: 11103850Abstract: The present application provides a graphite-like crystallite-based carbon nanomaterial, and a preparation method and application thereof. The graphite-like crystallite-based carbon nanomaterial provided by the present invention is a carbon nanomaterial having graphite-like crystallites as structural units, and includes, based on 100 parts by mass of chemical composition, 50-60 parts of carbon, 30-50 parts of oxygen, and 1-3 parts of hydrogen, where the structural units of the graphite-like crystallite-based carbon nanomaterial are the graphite-like crystallites; the size of the graphite-like crystallite-based carbon nanomaterial is 5-10 nm; and the graphite-like crystallite-based carbon nanomaterial is a non-fluorescent carbon nanomaterial.Type: GrantFiled: December 8, 2017Date of Patent: August 31, 2021Inventors: Songlin Zuo, Meng Miao, Yunyang Zhao
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Publication number: 20200384438Abstract: The present application provides a graphite-like crystallite-based carbon nanomaterial, and a preparation method and application thereof. The graphite-like crystallite-based carbon nanomaterial provided by the present invention is a carbon nanomaterial having graphite-like crystallites as structural units, and includes, based on 100 parts by mass of chemical composition, 50-60 parts of carbon, 30-50 parts of oxygen, and 1-3 parts of hydrogen, where the structural units of the graphite-like crystallite-based carbon nanomaterial are the graphite-like crystallites; the size of the graphite-like crystallite-based carbon nanomaterial is 5-10 nm; and the graphite-like crystallite-based carbon nanomaterial is a non-fluorescent carbon nanomaterial.Type: ApplicationFiled: December 8, 2017Publication date: December 10, 2020Applicant: Nanjing Forestry UniversityInventors: Songlin Zuo, Meng Miao, Yunyang Zhao