Abstract: An encoding and decoding method for an optical isolation amplifier including an encoder, an optical driver, a light source, an optical detector, and a decoder, and employing sigma-delta modulation technology is provided. The method includes: generating a plurality of first pulses, each having a predetermined pulse width, through the encoder when an input digital signal experiences an input pulse rising or falling edge; outputting an encoded signal having the plurality of first pulses to the optical driver; driving the light source through the optical driver, according to the plurality of first pulses, so as to output an encoded optical signal; generating a detected signal through the optical detector detecting the encoded optical signal, and the detected signal has a plurality of second pulses; and duplicating the input digital signal of the encoder through the decoder, according to the detected signal having the plurality of second pulses.

Abstract: A comparator circuit includes a first comparator, a second comparator and an inverter. The first comparator includes two N-channel metal-oxide-semiconductor (NMOS) transistors, two first P-channel metal-oxide-semiconductor (PMOS) transistors and two second PMOS transistors. A gate of the NMOS transistors respectively receives first and second voltages, and sources of the first PMOS transistors are connected to first and second resistors, respectively. The first comparator outputs differential output signals from drains of the NMOS transistors according to the voltage difference between the first and second voltages. An output of the second comparator is connected to gates of the first PMOS transistors of the first comparator. An input of the inverter is connected to the output of the second comparator, and an output of the inverter is connected to gates of the PMOS transistors.

Abstract: Disclosed is a differential transimpedance amplifier (TIA). In the differential TIA, an input end of the first source follower is coupled to the first output end of a first differential amplification circuit. The output end of the first source follower is coupled to the second input end of a second differential amplification circuit with feedback and a first feedback resistor. The input end of a second source follower is coupled to the second output end of the first differential amplification circuit. The output end of the second source follower is coupled to the first input end of the second differential amplification circuit with feedback and a second feedback resistor. A photo diode and a dummy diode are coupled respectively to two input ends of the first differential amplification circuit.

Abstract: Disclosed is a differential transimpedance amplifier (TIA). In the differential TIA, an input end of the first source follower is coupled to the first output end of a first differential amplification circuit. The output end of the first source follower is coupled to the second input end of a second differential amplification circuit with feedback and a first feedback resistor. The input end of a second source follower is coupled to the second output end of the first differential amplification circuit. The output end of the second source follower is coupled to the first input end of the second differential amplification circuit with feedback and a second feedback resistor. A photo diode and a dummy diode are coupled respectively to two input ends of the first differential amplification circuit.

Abstract: A buffer circuit receives a working supply voltage which may vary within a voltage range. The buffer circuit has a high voltage constant current buffer circuit, and in this circuit, the source of the first NMOS transistor is grounded, and drains of the first NMOS transistor and the first PMOS transistor are connected. The source of the second PMOS transistor is connected to the supply voltage input of the buffer circuit, and the drain of the second PMOS transistor is connected to the source of the first PMOS transistor. The input end of the high voltage diode connected composite transistors is connected to the supply voltage input of the buffer circuit, and the output end of the diode connected transistors is connected to the gates of first and second PMOS transistors. The first PMOS and NMOS transistors are high-voltage transistors. The second PMOS transistor is a low-voltage transistor.

Abstract: A low-dropout shunt voltage regulator is provided, which includes a first current mirror module, a second current mirror module and an output module. A first terminal of the first current mirror module is electrically connected to the input voltage. The first current mirror module has high output resistance. A first terminal of the second current mirror module is electrically connected to a second terminal of the first current mirror module. A second terminal of the second current mirror module is electrically connected to a reference voltage. An output terminal of the output module is electrically connected to the third terminal of the first current mirror module. The output terminal and a first terminal of the output module are both connected to the second current mirror module. A second terminal of the output module is electrically connected to the reference voltage.

Abstract: A buffer circuit receives a working supply voltage which may vary within a voltage range. The buffer circuit has a high voltage constant current buffer circuit, and in this circuit, the source of the first NMOS transistor is grounded, and drains of the first NMOS transistor and the first PMOS transistor are connected. The source of the second PMOS transistor is connected to the supply voltage input of the buffer circuit, and the drain of the second PMOS transistor is connected to the source of the first PMOS transistor. The input end of the high voltage diode connected composite transistors is connected to the supply voltage input of the buffer circuit, and the output end of the diode connected transistors is connected to the gates of first and second PMOS transistors. The first PMOS and NMOS transistors are high-voltage transistors. The second PMOS transistor is a low-voltage transistor.

Abstract: Disclosed is a transimpedance amplifier, comprising a first-stage trans-conductance amplifier TCA, a second-stage TCA, a third-stage amplifier and a feedback circuit. The first-stage TCA is electrically connected to an input current source to receive a first input signal, and outputs a first output signal. The second-stage TCA is electrically connected to the first-stage TCA to receive the first output signal, and outputs a second output signal. The third-stage amplifier is electrically connected to the second-stage TCA to receive the second output signal, and outputs a third output signal. One end of the feedback circuit is electrically connected to the input of the first-stage TCA, and the other end of the feedback circuit is electrically connected to the output of the third-stage amplifier to stabilize the third output signal. The third-stage amplifier is composed of a first output stage and a second output stage.

Abstract: A motor driver circuit for a Micro-electro-mechanical systems (MEMS) micro-mirror device, the motor driver circuit comprising: a non-inverting buffer circuit; an inverting buffer circuit; and a scalar circuit, the scalar circuit comprising a Supply Tracked Common Mode Voltage (VCMSC) generation circuit, wherein the non-inverting buffer circuit, the inverting buffer circuit, and the scalar circuit are configured, together with the VCMSC generation circuit, to provide a common mode voltage to a motor in response to a VCMSC voltage generated by the VCMSC generation circuit, and wherein the VCMSC voltage is generated by the VCMSC generation circuit in response to a control supply voltage and a driver supply voltage provided to the VCMSC generation circuit.

Abstract: A motor driver circuit for a Micro-electro-mechanical systems (MEMS) micro-mirror device, the motor driver circuit comprising: a non-inverting buffer circuit; an inverting buffer circuit; and a scalar circuit, the scalar circuit comprising a Supply Tracked Common Mode Voltage (VCMSC) generation circuit, wherein the non-inverting buffer circuit, the inverting buffer circuit, and the scalar circuit are configured, together with the VCMSC generation circuit, to provide a common mode voltage to a motor in response to a VCMSC voltage generated by the VCMSC generation circuit, and wherein the VCMSC voltage is generated by the VCMSC generation circuit in response to a control supply voltage and a driver supply voltage provided to the VCMSC generation circuit.