Abstract: The present disclosure is directed to methods and devices for devices including multiple die. A wafer is received having a plurality of die and a plurality of scribe lines. A dicing process is performed on the wafer. The dicing process includes identifying a first scribe line of the plurality of scribe lines, the first scribe line interposing a first die and a second die of the plurality of die; and performing a partial cut on the first scribe line. In embodiments, other scribe lines of the wafer are, during the dicing process, fully cut. After the dicing, the first die and the second die are mounted on a substrate such as an interposer. The first die and the second die are connected by a portion of the first scribe line, e.g., remaining from the partial cut, during the mounting.

Abstract: An integrated circuit package includes an interposer, the interposer including: a first redistribution layer, a second redistribution layer over the first redistribution layer in a central region of the interposer, a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view, a third redistribution layer over the second redistribution layer and the dielectric layer, and a first direct via extending through the dielectric layer. A conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via.

Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.

Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The first overlay grating has a first strip portion and a second strip portion, and the first strip portion and the second strip portion are elongated in a first elongated axis and are spaced apart from each other. The method includes forming a layer over the first overlay grating. The layer has a first trench elongated in a second elongated axis, the second elongated axis is substantially perpendicular to the first elongated axis, and the first trench extends across the first strip portion and the second strip portion. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The first overlay grating has a first strip portion and a second strip portion, and the first strip portion and the second strip portion are elongated in a first elongated axis and are spaced apart from each other. The method includes forming a layer over the first overlay grating. The layer has a first trench elongated in a second elongated axis, the second elongated axis is substantially perpendicular to the first elongated axis, and the first trench extends across the first strip portion and the second strip portion. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The method includes forming a layer over the first overlay grating. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion, the third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other, there is a second distance between a third sidewall of the third strip portion and a fourth sidewall of the fourth strip portion, the third sidewall faces away from the fourth strip portion, the fourth sidewall faces the third strip portion, the first distance is substantially equal to the second distance, and the first trench extends across the third strip portion and the fourth strip portion.

Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The method includes forming a layer over the first overlay grating. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion, the third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other, there is a second distance between a third sidewall of the third strip portion and a fourth sidewall of the fourth strip portion, the third sidewall faces away from the fourth strip portion, the fourth sidewall faces the third strip portion, the first distance is substantially equal to the second distance, and the first trench extends across the third strip portion and the fourth strip portion.

Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The first overlay grating has a first strip portion and a second strip portion. The method includes forming a first layer over the first overlay grating. The first layer has a first trench elongated in a second elongated axis, the second elongated axis is substantially perpendicular to the first elongated axis, and the first trench extends across the first strip portion and the second strip portion. The method includes forming a second overlay grating over the first layer. The second overlay grating has a third strip portion and a fourth strip portion. The third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The first overlay grating has a first strip portion and a second strip portion. The method includes forming a first layer over the first overlay grating. The first layer has a first trench elongated in a second elongated axis, the second elongated axis is substantially perpendicular to the first elongated axis, and the first trench extends across the first strip portion and the second strip portion. The method includes forming a second overlay grating over the first layer. The second overlay grating has a third strip portion and a fourth strip portion. The third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other.

Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.

Abstract: The present disclosure provides a method. The method includes forming a resist layer on a patterned substrate; collecting first overlay data from the patterned substrate; determining an overlay compensation based on mapping of second overlay data from an integrated circuit (IC) pattern to the first overlay data from the patterned substrate; performing a compensation process to a lithography system according to the overlay compensation; and thereafter performing a lithography exposing process to the resist layer by the lithography system, thereby imaging the IC pattern to the resist layer.

Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.

Abstract: Provided is a material composition and method for inhibiting the printing of SRAFs onto a substrate including coating a substrate with a resist layer. After coating the substrate, the resist layer is patterned to form a main feature pattern and at least one sub-resolution assist feature (SRAF) pattern within the resist layer. The main feature pattern may include resist sidewalls and a portion of a layer underlying the patterned resist layer. In various examples, a material composition is deposited over the patterned resist layer and into each of the main feature pattern and the at least one SRAF pattern. Thereafter, a material composition development process is performed to dissolve a portion of the material composition within the main feature pattern and to expose the portion of the layer underlying the patterned resist layer.

Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.

Abstract: The present disclosure provides a method. The method includes forming a resist layer on a patterned substrate; collecting first overlay data from the patterned substrate; determining an overlay compensation based on mapping of second overlay data from an integrated circuit (IC) pattern to the first overlay data from the patterned substrate; performing a compensation process to a lithography system according to the overlay compensation; and thereafter performing a lithography exposing process to the resist layer by the lithography system, thereby imaging the IC pattern to the resist layer.

Abstract: An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.

Abstract: An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.