Abstract: A semiconductor power device includes a substrate, a first semiconductor layer on the substrate, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer. At least a recessed epitaxial structure is disposed within a cell region and the recessed epitaxial structure may be formed in a pillar or stripe shape. A first vertical diffusion region is disposed in the third semiconductor layer and the recessed epitaxial structure is surrounded by the first vertical diffusion region. A source conductor is disposed on the recessed epitaxial structure and a trench isolation is disposed within a junction termination region surrounding the cell region. In addition, the trench isolation includes a trench, a first insulating layer on an interior surface of the trench, and a conductive layer filled into the trench, wherein the source conductor connects electrically with the conductive layer.

Abstract: A super junction transistor includes a drain substrate, an epitaxial layer, wherein the epitaxial layer is disposed on the drain substrate, a plurality of gate structure units embedded on the surface of the epitaxial layer, a plurality of trenches disposed in the epitaxial layer between the drain substrate and the gate structure units, a buffer layer in direct contact with the inner surface of the trenches, a plurality of body diffusion regions with a first conductivity type adjacent to the outer surface of the trenches, wherein there is at least a PN junction on the interface between the body diffusion region and the epitaxial layer, and a doped source region, wherein the doped source region is disposed in the epitaxial layer and is adjacent to the gate structure unit.

Abstract: A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.

Abstract: A termination structure for a power MOSFET device includes a substrate, an epitaxial layer on the substrate, a trench in the epitaxial layer, a first insulating layer within the trench, a first conductive layer atop the first insulating layer, and a column doping region in the epitaxial layer and in direct contact with the first conductive layer. The first conductive layer is in direct contact with the first insulating layer and is substantially level with a top surface of the epitaxial layer. The first conductive layer comprises polysilicon, titanium, titanium nitride or aluminum.

Abstract: A semiconductor device includes: a substrate including a first epitaxial layer that has a first electrical type, and a second epitaxial layer; a transistor that includes a source region and an insulating spacer; an inner surrounding structure including an annular trench and an insulating spacer; an outer surrounding structure that has a second electrical type opposite to the first electrical type, and that is disposed adjacent to an upper surface of the second epitaxial layer to surround and contact the inner surrounding structure; and a conductive structure connecting to the source region, and the inner and outer surrounding structures.

Abstract: A method for fabricating a power transistor includes: (a) forming a trench in a substrate with a first electrical type; (b) diffusing second electrical type carriers into the substrate from the trench such that the substrate is formed into a first part and a second part that is diffused with the second electrical type carriers and that adjoins the trench, the first and second parts being crystal lattice continuous to each other; (c) forming a filling portion in the trench, the filling portion adjoining the second part; (d) performing a carrier-implanting process in the second part and the filling portion; and (e) forming over the substrate a gate structure that has a dielectric layer and a conductive layer.

Abstract: A semiconductor device having a super junction includes: a substrate having a first electrical type; a main body including a base part that has the first electrical type, and a modified part that has a second electrical type opposite to the first electrical type; a source zone contacting the modified part oppositely of the substrate, and having the first electrical type; and a gate structure having a dielectric layer that contacts the source zone, and a conductive layer formed on the dielectric layer oppositely of the main body.

Abstract: An insulated gate bipolar transistor includes: a collector layer; a drift layer formed on and connected to the collector layer; a gate structure including a dielectric layer formed on the drift layer, and a conductive layer formed on the dielectric layer; a first emitter structure including a well region formed within the drift layer and partially connected to the dielectric layer of the gate structure, a source region formed within the well region just underneath a top surface of the well region, and a first electrode formed on the top surface of the well region and connected to the well region and the source region; and a second emitter structure spaced apart from the gate structure and the first emitter structure, and including a bypass region formed on the top surface of the drift layer, and a second electrode formed on the bypass region.

Abstract: A method for forming a power device includes the following steps. An epitaxial layer is formed on a substrate. A pad layer and hard mask are formed on the epitaxial layer. A trench is etched into the hard mask, the pad layer, and the epitaxial layer. The hard mask is removed. A buffer layer is formed on the sidewall of the trench. The trench is then filled with a dopant source layer comprising plural dopants. A drive-in process is performed to diffuse the dopants into the epitaxial layer through the buffer layer, thereby forming a diffusion region around the trench.

Abstract: A method for fabricating a semiconductor device having a dual damascene opening structure. The method includes the steps of providing a substrate having a dielectric layer thereon. A first photoresist layer having a via contact hole pattern is formed on the dielectric layer. A sacrificial layer is formed on the first photoresist layer and fills up the via contact hole pattern. A second photoresist layer having an interconnect trench pattern is formed on the sacrificial layer, thereby exposing the sacrificial layer beneath the interconnect trench pattern. The interconnect trench pattern is transferred to the sacrificial layer using the second photoresist layer as a mask.

Abstract: A method for fabricating a semiconductor device having a dual damascene opening structure. The method includes the steps of providing a substrate having a dielectric layer thereon. A first photoresist layer having a via contact hole pattern is formed on the dielectric layer. A sacrificial layer is formed on the first photoresist layer and fills up the via contact hole pattern. A second photoresist layer having an interconnect trench pattern is formed on the sacrificial layer, thereby exposing the sacrificial layer beneath the interconnect trench pattern. The interconnect trench pattern is transferred to the sacrificial layer using the second photoresist layer as a mask.