Patents by Inventor Meng-Yi Wu
Meng-Yi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160005860Abstract: In a method for manufacturing a semiconductor device, a substrate including a gate structure is provided. A source region and a drain region are formed at opposing sides of the gate structure and an implant region for a resistor device is formed in the substrate. Pocket implant regions are formed in the source region and the drain region. A dielectric layer is formed to cover the gate structure and the substrate. A portion of dopants in the pocket implant regions interact with portions of dopants in the source region and the drain region to form lightly doped drain regions above the pocket implant regions. A resistor region of the resistor device is defined on the implant region. A portion of the dielectric layer is removed to form a spacer on a sidewall of the gate structure and a resistor protection dielectric layer on a portion of the implant region.Type: ApplicationFiled: July 1, 2014Publication date: January 7, 2016Inventors: Ming-Chi WU, Yu-Lung YEH, Chieh-Shuo LIANG, Shih-Chang LIN, Meng-Yi WU, Hsing-Chih LIN
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Patent number: 9224497Abstract: The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal.Type: GrantFiled: April 28, 2015Date of Patent: December 29, 2015Assignee: eMemory Technology Inc.Inventors: Meng-Yi Wu, Chih-Hao Huang, Hsin-Ming Chen
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Publication number: 20150287730Abstract: An OTP memory cell including an antifuse unit and a select transistor is provided. The antifuse unit includes an antifuse layer and an antifuse gate disposed on a substrate in sequence, a modified extension doped region disposed in the substrate below the antifuse layer, and a first doped region and a second doped region disposed in the substrate at two opposite sides of the antifuse gate. The select transistor includes a select gate, a gate dielectric layer, a second doped region, and a third doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The second and the third doped region are respectively disposed in the substrate at two opposite sides of the select gate. The doped region, the antifuse layer and the antifuse gate form a varactor.Type: ApplicationFiled: January 27, 2015Publication date: October 8, 2015Inventors: Meng-Yi Wu, Hsin-Ming Chen, Chun-Hung Lu
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Publication number: 20150243366Abstract: The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal.Type: ApplicationFiled: April 28, 2015Publication date: August 27, 2015Inventors: Meng-Yi Wu, Chih-Hao Huang, Hsin-Ming Chen
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Patent number: 9013910Abstract: Provided is an OTP memory cell including a first antifuse unit, a second antifuse unit, a select transistor, and a well region. The first and the second antifuse unit respectively include an antifuse layer and an antifuse gate disposed on a substrate in sequence. The select transistor includes a select gate, a gate dielectric layer, a first doped region, and a second doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The first and the second doped region are respectively disposed in the substrate at two sides of the select gate, wherein the second doped region is disposed in the substrate at the periphery of the first and the second antifuse unit. The well region is disposed in the substrate below the first and the second antifuse unit and is connected to the second doped region.Type: GrantFiled: December 10, 2013Date of Patent: April 21, 2015Assignee: eMemory Technology Inc.Inventors: Chin-Yi Chen, Lun-Chun Chen, Yueh-Chia Wen, Meng-Yi Wu, Hsin-Ming Chen
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Publication number: 20140340955Abstract: The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal.Type: ApplicationFiled: March 24, 2014Publication date: November 20, 2014Applicant: eMemory Technology Inc.Inventors: Meng-Yi Wu, Chih-Hao Huang, Hsin-Ming Chen
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Patent number: 8861250Abstract: A novel mask read-only memory is provided. After the mask read-only memory leaves the factory, the mask read-only memory has two types of cell structures. The first type cell structure records a first storing state (e.g. the logic state “1”), and the second type cell structure records a second storing state (the logic state “0”).Type: GrantFiled: July 31, 2013Date of Patent: October 14, 2014Assignee: eMemory Technology Inc.Inventors: Meng-Yi Wu, Chih-Hao Huang, Kuan-Ming Huang
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Publication number: 20140293673Abstract: A nonvolatile memory cell structure includes a doping well disposed in a substrate, an antifuse gate disposed on the doping well, a drain disposed in the substrate, an optional select gate disposed on the doping well and an optional shallow trench isolation disposed inside the doping well.Type: ApplicationFiled: February 10, 2014Publication date: October 2, 2014Applicant: eMemory Technology Inc.Inventors: Meng-Yi Wu, Chih-Hao Huang, Yueh-Chia Wen, Chin-Yi Chen, Lun-Chun Chen, Hsin-Ming Chen
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Publication number: 20140098591Abstract: Provided is an OTP memory cell including a first antifuse unit, a second antifuse unit, a select transistor, and a well region. The first and the second antifuse unit respectively include an antifuse layer and an antifuse gate disposed on a substrate in sequence. The select transistor includes a select gate, a gate dielectric layer, a first doped region, and a second doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The first and the second doped region are respectively disposed in the substrate at two sides of the select gate, wherein the second doped region is disposed in the substrate at the periphery of the first and the second antifuse unit. The well region is disposed in the substrate below the first and the second antifuse unit and is connected to the second doped region.Type: ApplicationFiled: December 10, 2013Publication date: April 10, 2014Applicant: eMemory Technology Inc.Inventors: Chin-Yi Chen, Lun-Chun Chen, Yueh-Chia Wen, Meng-Yi Wu, Hsin-Ming Chen
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Patent number: 8681528Abstract: A one-bit memory cell for a nonvolatile memory includes a bit line and a plurality of serially-connected storage units. The bit line is connected to the serially-connected storage units. Each storage unit includes a first doped region, a second doped region and a third doped region, which are formed in a surface of a substrate. A first gate structure is disposed over a first channel region between the first doped region and the second doped region. The first gate structure is connected to a control signal line. A second gate structure is disposed over a second channel region between the second doped region and the third doped region. The second gate structure is connected to an anti-fuse signal line.Type: GrantFiled: August 21, 2012Date of Patent: March 25, 2014Assignee: eMemory Technology Inc.Inventors: Meng-Yi Wu, Yueh-Chia Wen, Hsin-Ming Chen, Ching-Sung Yang
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Patent number: 8664073Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.Type: GrantFiled: January 4, 2011Date of Patent: March 4, 2014Assignee: United Microelectronics Corp.Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Meng-Yi Wu, Tzyy-Ming Cheng
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Publication number: 20140056051Abstract: A one-bit memory cell for a nonvolatile memory includes a bit line and a plurality of serially-connected storage units. The bit line is connected to the serially-connected storage units. Each storage unit includes a first doped region, a second doped region and a third doped region, which are formed in a surface of a substrate. A first gate structure is disposed over a first channel region between the first doped region and the second doped region. The first gate structure is connected to a control signal line. A second gate structure is disposed over a second channel region between the second doped region and the third doped region. The second gate structure is connected to an anti-fuse signal line.Type: ApplicationFiled: August 21, 2012Publication date: February 27, 2014Applicant: eMemory Technology Inc.Inventors: Meng-Yi Wu, Yueh-Chia Wen, Hsin-Ming Chen, Ching-Sung Yang
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Publication number: 20130121079Abstract: The present invention provides a NOR flash memory cell. The NOR flash memory cell includes a first transistor, a second transistor and at least one third transistor. The first transistor has a control terminal, a first terminal and a second terminal. The control terminal used to receive a word line signal and the first terminal used to receive a bit line signal. A gate of the first transistor comprises a silicon-rich nitride layer and an oxide layer, wherein the silicon-rich nitride layer is buried in the oxide layer. A control terminal of the second transistor used to receive a read signal. A second terminal of the second transistor used to transport a source line signal according to the read signal. The third transistor coupled between the first transistor and the bit line signal, and a control terminal of the third transistor receives a midway control signal.Type: ApplicationFiled: November 14, 2011Publication date: May 16, 2013Applicant: EMEMORY TECHNOLOGY INC.Inventors: Meng-Yi Wu, Ching-Sung Yang
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Publication number: 20130064027Abstract: By adjusting an operating voltage of a memory cell in a memory according to a measured capacitance result indicating capacitance of an under-test capacitor of the memory cell, an appropriate operating voltage for the memory cell can always be determined according to the measured capacitance result. The measured capacitance result indicates whether the capacitance of the under-test capacitor indicating the characteristic of the gate dielectric of the memory cell is higher or lower than a reference capacitor, and is generated by amplifying a difference between two voltages indicating capacitance of the reference capacitor and the capacitance of the under-test capacitor.Type: ApplicationFiled: September 14, 2011Publication date: March 14, 2013Inventors: Meng-Yi Wu, Wein-Town Sun, Yen-Tai Lin, Cheng-Jye Liu, Chiun-Chi Shen
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Patent number: 8222113Abstract: A method for forming a metal-oxide-semiconductor (MOS) device includes at least steps of forming a pair of trenches in a substrate at both sides of a gate structure, filling the trenches with a silicon germanium layer by a selective epitaxy growth process, forming a cap layer on the silicon germanium layer by a selective growth process, and forming a pair of source/drain regions by performing an ion implantation process. Hence, the undesirable effects caused by ion implantation can be mitigated.Type: GrantFiled: May 20, 2009Date of Patent: July 17, 2012Assignee: United Microelectronics Corp.Inventors: Shyh-Fann Ting, Shih-Chieh Hsu, Cheng-Tung Huang, Chih-Chiang Wu, Wen-Han Hung, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Kun-Hsien Lee, Tzyy-Ming Cheng
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Publication number: 20120009745Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.Type: ApplicationFiled: January 4, 2011Publication date: January 12, 2012Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Meng-Yi Wu, Tzyy-Ming Cheng
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Publication number: 20110104864Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.Type: ApplicationFiled: January 5, 2011Publication date: May 5, 2011Inventors: Li-Shian Jeng, Cheng-Tung Huang, Shyh-Fann Ting, Wen-Han Hung, Kun-Hsien Lee, Meng-Yi Wu, Tzyy-Ming Cheng
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Publication number: 20110097868Abstract: A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.Type: ApplicationFiled: January 4, 2011Publication date: April 28, 2011Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Meng-Yi Wu, Tzyy-Ming Cheng
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Patent number: 7927954Abstract: A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.Type: GrantFiled: February 26, 2007Date of Patent: April 19, 2011Assignee: United Microelectronics Corp.Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Li-Shian Jeng, Kun-Hsien Lee, Wen-Han Hung, Tzyy-Ming Cheng, Meng-Yi Wu, Tsai-Fu Hsiao, Shu-Yen Chan
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Patent number: 7888223Abstract: A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.Type: GrantFiled: March 28, 2007Date of Patent: February 15, 2011Assignee: United Microelectronics Corp.Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Meng-Yi Wu, Tzyy-Ming Cheng