Patents by Inventor Meng-Yueh Liu
Meng-Yueh Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220285552Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: Chia-Ling Chan, Meng-Yueh Liu, Wei-Ken Lin
-
Patent number: 11342454Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.Type: GrantFiled: June 22, 2020Date of Patent: May 24, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ling Chan, Meng-Yueh Liu, Wei-Ken Lin
-
Publication number: 20200321465Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.Type: ApplicationFiled: June 22, 2020Publication date: October 8, 2020Inventors: Chia-Ling Chan, Meng-Yueh Liu, Wei-Ken Lin
-
Patent number: 10700197Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.Type: GrantFiled: November 17, 2017Date of Patent: June 30, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ling Chan, Meng-Yueh Liu, Wei-Ken Lin
-
Publication number: 20190103491Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.Type: ApplicationFiled: November 17, 2017Publication date: April 4, 2019Inventors: Chia-Ling Chan, Meng-Yueh Liu, Wei-Ken Lin
-
Patent number: 9564321Abstract: A cyclic deposition and etch method is provided. The method includes depositing an epitaxial layer over a substrate at a first temperature and etching a portion of the deposited epitaxial layer at a variable temperature higher than the first temperature. The step of etching is performed while varying the temperature.Type: GrantFiled: March 11, 2013Date of Patent: February 7, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun Hsiung Tsai, Meng-Yueh Liu, Chien-Chang Su, Yuan-Feng Chao, Yuh-Da Fan
-
Patent number: 9502404Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown silicon-containing material without using GeH4 in an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.Type: GrantFiled: November 20, 2014Date of Patent: November 22, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Meng-Yueh Liu
-
Patent number: 9252008Abstract: The embodiments of mechanisms for monitoring thermal budget of an etch process of a cyclic deposition/etch (CDE) process to form an epitaxially grown silicon-containing material are descried to enable and to improve process control of the material formation. The monitoring is achieved by measuring the temperature of each processed wafer as a function of process time to calculate the accumulated thermal budget (ATB) of the wafer and to compare the ATB with a reference ATB (or optimal accumulated thermal budget, OATB) to see if the processed wafer is within an acceptable range (or tolerance). The results are used to determine whether to pass the processed wafer or to reject the processed wafer.Type: GrantFiled: January 11, 2013Date of Patent: February 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Meng-Yueh Liu, Kun-Hsiang Liao
-
Publication number: 20150076621Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown silicon-containing material without using GeH4 in an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.Type: ApplicationFiled: November 20, 2014Publication date: March 19, 2015Inventors: Chun Hsiung Tsai, Meng-Yueh Liu
-
Patent number: 8906789Abstract: The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed.Type: GrantFiled: April 30, 2013Date of Patent: December 9, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun Hsiung Tsai, Yi-Fang Pai, Chien-Chang Su, Tzu-Chun Tseng, Meng-Yueh Liu
-
Patent number: 8900958Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) descried enable forming an epitaxially grown silicon-containing material without using GeH4 in an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.Type: GrantFiled: December 19, 2012Date of Patent: December 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Meng-Yueh Liu
-
Publication number: 20140264348Abstract: The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed.Type: ApplicationFiled: April 30, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.Inventors: Chun Hsiung Tsai, Yi-Fang Pai, Chien-Chang Su, Tzu-Chun Tseng, Meng-Yueh Liu
-
Publication number: 20140256119Abstract: A cyclic deposition and etch method is provided. The method includes depositing an epitaxial layer over a substrate at a first temperature and etching a portion of the deposited epitaxial layer at a variable temperature higher than the first temperature. The step of etching is performed while varying the temperature.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun Hsiung TSAI, Meng-Yueh LIU, Chien-Chang SU, Yuan-Feng CHAO, Yuh-Da FAN
-
Publication number: 20090298259Abstract: As the conventional nanowire technology has many restrictions, the present invention discloses a method for transferring a one-dimensional micro/nanostructure to diversify the fabrication and application of nanocomponents, wherein a micro/nanostructure having formed on one substrate can be arbitrarily transferred to another substrate, whereby a micro/nanostructure can be integrated with different substrates.Type: ApplicationFiled: September 22, 2008Publication date: December 3, 2009Inventors: Ching-Fuh Ling, Shu-Chia Shiu, Chieh-Yu Hsiao, Meng-Yueh Liu