Abstract: Fingerprint identification modules, methods for forming the fingerprint identification modules and electronic devices are provided. The method may include providing a substrate, containing a signal process circuit formed therein; providing a carrier substrate; forming one or more piezoelectric transducers on the carrier substrate, wherein a piezoelectric transducer of the one or more piezoelectric transducers includes a first electrode, a piezoelectric layer on the first electrode and a second electrode on the piezoelectric layer; forming a permanent bonding layer, containing one or more cavities, on one of the carrier substrate and the substrate; bonding the carrier substrate with the substrate using the permanent bonding layer, wherein the permanent bonding layer is between the one or more piezoelectric transducers and the substrate, and each piezoelectric transducer covers one cavity; and removing the carrier substrate.

Abstract: A package structure of an air gap type semiconductor device includes a carrier; a semiconductor chip; and a bonding layer disposed between the carrier and the semiconductor chip. A first cavity is formed in the bonding layer and enclosed by the semiconductor chip and the carrier to at least aligned with a portion of an active region of the semiconductor chip. An encapsulation layer and the bonding layer are on a same side of the carrier to encapsulate the semiconductor chip and an exposed region of the bonding layer. At least one portion of the encapsulation layer is formed between the semiconductor chip and the carrier along a direction perpendicular to a lateral surface of the carrier. Interconnection structures formed on a side of the carrier different from a side with the bonding layer. Each interconnection structure is electrically connected to a corresponding input/output electrode of the semiconductor chip.

Abstract: The present disclosure provides a package structure of an air gap type semiconductor device and its fabrication method. The fabrication method includes forming a bonding layer having a first opening on a carrier; disposing a semiconductor chip on the bonding layer, thereby forming a first cavity at the first opening, where the first cavity is at least aligned with a portion of an active region of the semiconductor chip; performing an encapsulation process to encapsulate the semiconductor chip on the carrier; lastly, forming through holes passing through the carrier where each through hole is aligned with a corresponding input/output electrode region of the semiconductor chip, and forming interconnection structures on a side of the carrier different from a side with the bonding layer, where each interconnection structure passes through a corresponding through hole and is electrically connected to an corresponding input/output electrode.

Abstract: The present disclosure provides a mask plate and fabrication method thereof. The mask plate includes a substrate, having a first surface and a second surface, and containing a plurality of openings. The mask plate also includes a mask pattern layer, formed on the first surface of the substrate and including a plurality of pattern regions and a shield region surrounding the plurality of pattern regions. Each pattern region includes at least one through hole, and each opening formed in the substrate exposes a pattern region and the at least one through hole in the pattern region. The mask plate further includes a top substrate layer, formed on the mask pattern layer. The top substrate layer contains a plurality of grooves passing through the top substrate layer, and each groove exposes a pattern region in the mask pattern layer and exposes the at least one through hole in the pattern region.

Abstract: An image capturing assembly includes an encapsulation layer, embedded with functional components. The top surface and bottom surface of the encapsulation layer expose the functional components. A through hole is formed in the encapsulation layer; and the functional components have soldering pads facing away from a bottom of the encapsulation layer. A photosensitive unit including a photosensitive chip and an optical filter is mounted on the photosensitive chip. The photosensitive chip is embedded in the through hole; the optical filter is outside the through hole; the top surface and bottom surface of the encapsulation layer expose the photosensitive chip; and the photosensitive chip includes soldering pads facing away from the bottom of the encapsulation layer. A redistribution layer structure is on the top side of the encapsulation layer and electrically connects the soldering pads of the photosensitive chip with the soldering pads of the functional components.

Abstract: A wafer-level system-in-package (WLSiP) package structure is provided. The WLSiP package structure includes a device wafer, an adhesive layer, and a plurality of second chips. The device wafer includes a first front surface having a plurality of first chips integrated therein and a first back surface opposing the first front surface. The adhesive layer is formed on the first front surface of the device wafer and the adhesive layer includes a plurality of through-holes exposing the first front surface. The plurality of second chips are bonded to the device wafer, and the plurality of second chips are bonded with the adhesive layer to cover the plurality of first through-holes in a one-to-one correspondence.

Abstract: The present disclosure provides an image capturing assembly and its packaging method, a lens module and an electronic device. The packaging method includes: providing a photosensitive chip; mounting an optical filter on the photosensitive chip; providing a carrier substrate and temporarily bonding the photosensitive chip and functional components on the carrier substrate; and forming an encapsulation layer on the carrier substrate and at least between the photosensitive chip and the functional components.

Abstract: The present disclosure provides a camera assembly, a lens module, and an electronic device. The camera assembly includes a photosensitive unit, functional components, a redistribution layer (RDL) structure, and an encapsulation layer, embedded with the photosensitive unit, the functional components, and the RDL structure. The photosensitive unit includes a photosensitive chip and an optical filter mounted on the photosensitive chip. The RDL structure and the optical filter are exposed from a top surface of the encapsulation layer. A highest top of the photosensitive chip and the functional components is exposed from a bottom surface of the encapsulation layer. The photosensitive chip and the functional components have solder pads facing the RDL structure and electrically connecting with the RDL structure.

Abstract: The present disclosure provides a camera assembly and a packaging method thereof, a lens module, and an electronic device.

Abstract: A camera assembly includes a photosensitive unit, including a photosensitive chip and an optical filter mounted on the photosensitive chip; functional components; and an encapsulation layer, embedded with the photosensitive unit and the functional components. The photosensitive chip and the functional components are exposed from a bottom surface of the encapsulation layer. A top surface of the encapsulation layer is higher than the photosensitive chip and functional components and exposes the optical filter. The photosensitive chip has soldering pads facing away from the bottom surface of the encapsulation layer. The functional components have soldering pads exposed from the bottom surface of the encapsulation layer. The camera assembly further includes a redistribution layer structure, disposed on the bottom surface of the encapsulation layer and electrically connecting to the soldering pads.

Abstract: A semiconductor device is provided. The semiconductor device includes: a plurality of alignment dies, each including a diced first base substrate and at least one alignment mark on the diced first base substrate; a second base substrate; and a bonding film on the second base substrate. An alignment die of the plurality of alignment dies are attached on the bonding film on an alignment region of the second base substrate for aligning the second base substrate.

Abstract: The present disclosure provides a method for packaging a camera assembly. The method includes: providing a photosensitive chip; mounting an optical filter on the photosensitive chip; temporarily bonding the photosensitive chip and functional components on a carrier substrate, where the photosensitive chip has soldering pads facing away from the carrier substrate and the functional components have soldering pads facing toward the carrier substrate; forming an encapsulation layer covering the carrier substrate, the photosensitive chip, and the functional components, and exposing the optical filter; after the encapsulation layer is formed, removing the carrier substrate; and after the carrier substrate is removed, forming a redistribution layer structure on a side of the encapsulation layer facing away from the optical filter to electrically connect the soldering pads of the photosensitive chip with the soldering pads of the functional components.

Abstract: An alignment mark, a semiconductor device, and fabrication methods of the alignment mark and the semiconductor device are provided. The method includes providing a first base substrate, and forming a plurality of alignment marks on the first base substrate. The method also includes dicing the first base substrate to form a plurality of alignment dies. Each alignment die includes a diced first base substrate and at least one alignment mark diced from the plurality of alignment marks on the diced first base substrate. In addition, the method includes providing a second base substrate for aligning, and forming a bonding film on the second base substrate. Further, the method includes attaching an alignment die of the plurality of alignment dies to the bonding film on an alignment region of the second base substrate using a die attach process.

Abstract: Fingerprint identification modules, methods for forming the fingerprint identification modules and electronic devices are provided. The method may include providing a substrate, containing a signal process circuit formed therein; providing a carrier substrate; forming one or more piezoelectric transducers on the carrier substrate, wherein a piezoelectric transducer of the one or more piezoelectric transducers includes a first electrode, a piezoelectric layer on the first electrode and a second electrode on the piezoelectric layer; forming a permanent bonding layer, containing one or more cavities, on one of the carrier substrate and the substrate; bonding the carrier substrate with the substrate using the permanent bonding layer, wherein the permanent bonding layer is between the one or more piezoelectric transducers and the substrate, and each piezoelectric transducer covers one cavity; and removing the carrier substrate.

Abstract: An image capturing assembly includes an encapsulation layer, embedded with functional components. The top surface and bottom surface of the encapsulation layer expose the functional components. A through hole is formed in the encapsulation layer; and the functional components have soldering pads facing away from a bottom of the encapsulation layer. A photosensitive unit including a photosensitive chip and an optical filter is mounted on the photosensitive chip. The photosensitive chip is embedded in the through hole; the optical filter is outside the through hole; the top surface and bottom surface of the encapsulation layer expose the photosensitive chip; and the photosensitive chip includes soldering pads facing away from the bottom of the encapsulation layer. A redistribution layer structure is on the top side of the encapsulation layer and electrically connects the soldering pads of the photosensitive chip with the soldering pads of the functional components.

Abstract: The present disclosure provides a wafer-level system-in-package (WLSiP) packaging method and a WLSiP package structure. The WLSiP package structure includes a device substrate including a substrate and a plurality of first chips on the substrate, an encapsulation layer, covering the device substrate, a plurality of second chips embedded in the encapsulation; and an electrical connection structure, electrically connecting at least one of the plurality of second chips with at least one of the plurality of first chips. The plurality of first chips and the plurality of second chips are staggered from each other.

Abstract: A wafer-level system-in-package (WLSiP) package structure is provided. The WLSiP package structure includes a device wafer, an adhesive layer, and a plurality of second chips. The device wafer includes a first front surface having a plurality of first chips integrated therein and a first back surface opposing the first front surface. The adhesive layer is formed on the first front surface of the device wafer and the adhesive layer includes a plurality of through-holes exposing the first front surface. The plurality of second chips are bonded to the device wafer, and the plurality of second chips are bonded with the adhesive layer to cover the plurality of first through-holes in a one-to-one correspondence.

Abstract: The present disclosure provides a method for packaging a camera assembly. The method includes providing a photosensitive chip having a plurality of first soldering pads; mounting a filter on the photosensitive chip; providing a first carrier substrate; and bonding a plurality of functional components and the photosensitive chip to the first carrier substrate. The plurality of functional components has a plurality of second soldering pads, and the first soldering pads and the second soldering pads all face away from the first carrier substrate. The method includes forming an encapsulation layer to cover the first carrier substrate, the photosensitive chip, and the functional components. The encapsulation layer exposes the filter. The method further includes forming a redistribution layer structure, on one side of the encapsulation layer close to the filter, to electrically connect to the first soldering pads and the second soldering pads; and removing the first carrier substrate.

Abstract: A wafer-level system-in-package (WLSiP) packaging method and a WLSiP package structure are provided. The method includes providing a device wafer including a first front surface and a first back surface and providing a plurality of second chips. The method also includes forming an adhesive layer on the first front surface and patterning the adhesive layer to form a plurality of first through-holes. In addition, the method includes bonding the plurality of second chips with a remaining adhesive layer to cover the plurality of first through-holes. Moreover, the method includes forming a plurality of second through-holes, which are connected with the plurality of first through-holes to form a plurality of first conductive through-holes, each first conductive through-hole includes a second through-hole and a first through-hole. Further, the method includes forming a first conductive plug in a first conductive through-hole to electrically connect to one of the plurality of second chips.

Abstract: An image capturing assembly and its packaging method are provided. The method includes: providing a photosensitive chip having soldering pads and a mounted optical filter; bonding functional components on a provided first carrier substrate temporarily, where the functional components have soldering pads facing away from or facing toward the first carrier substrate; forming an encapsulation layer at least being filled between the functional components on the first carrier substrate, and forming a through hole in the encapsulation layer; placing the photosensitive chip in the through hole and bonding the photosensitive chip on the first carrier substrate temporarily, where the soldering pads of the photosensitive chip face away from the first carrier substrate; and after the photosensitive chip is temporarily bonded on the first carrier substrate, forming a redistribution layer structure to electrically connect the soldering pads of the photosensitive chip with the soldering pads of the functional components.