Abstract: Systems and methods for network traffic metering credit distribution and packet processing in a network device having multiple processing units are provided. According to an embodiment, management of multiple meters is distributed among multiple processing units of a network device. Each meter is implemented in a form of a master entry and a slave entry. Responsive to receipt by one of the processing units of a packet subject to rate-limiting by a meter, an action to be taken on the packet is made with reference to a slave entry managed by the processing unit based on available credit of the slave entry. When the action indicates the packet is to be passed: (i) credits associated with passing the packet are deducted from the available credit; and (ii) the packet is passed to a subsequent stage of packet processing; otherwise, the packet is dropped.

Abstract: Systems and methods for network traffic metering credit distribution and packet processing in a network device having multiple processing units are provided. According to an embodiment, management of multiple meters is distributed among multiple processing units of a network device. Each meter is implemented in a form of a master entry and a slave entry. Responsive to receipt by one of the processing units of a packet subject to rate-limiting by a meter, an action to be taken on the packet is made with reference to a slave entry managed by the processing unit based on available credit of the slave entry. When the action indicates the packet is to be passed: (i) credits associated with passing the packet are deducted from the available credit; and (ii) the packet is passed to a subsequent stage of packet processing; otherwise, the packet is dropped.

Abstract: An iterative mantissa calculator calculates a quotient mantissa for a divide mode or a result mantissa for a square-root mode. The calculator includes at least first and second summing devices. In the divide mode, each summing device calculates a respective estimated partial remainder W[j+1] for the next iteration, j+1, as 2*W[j]?Sj+1*D, where W[j] is the estimated partial remainder for the current iteration calculated during the prior iteration, Sj+1 is the quotient bit estimated for the next iteration, and D is the respective divisor bit. The estimated quotient bit for the next iteration is selected based on the calculated partial remainder. In the square-root mode, the first summing device calculates 2W[j]?2S[j]Sj+1, where W[j] is the estimated partial remainder and Sj+1 is the estimated result generated during the current iteration, j.