Patents by Inventor Mengchen Yu

Mengchen Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240386543
    Abstract: A fatigue crack propagation rate test device and method based on deep learning, comprises a dual scale Faster Region-based Convolutional Neural Network (Faster-RCNN) to accurately measure a crack length. The device can be used for tracking a crack propagation length of a non-standard test-piece having any geometric size. The method comprises: firstly, acquiring crack data sets of different scales by means of a camera; secondly, training the crack data sets by using the Faster-RCNN; then, constructing a global and local dual scale fast convolutional neural network, and predicting crack lengths under whole times of load cycle; and finally, fusing fracture mechanics to obtain a relationship between the fatigue crack propagation rate and a crack tip stress intensity factor.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Inventors: Xiangyun Long, Chao Jiang, Mengchen Yu
  • Patent number: 11483241
    Abstract: Systems and methods for network traffic metering credit distribution and packet processing in a network device having multiple processing units are provided. According to an embodiment, management of multiple meters is distributed among multiple processing units of a network device. Each meter is implemented in a form of a master entry and a slave entry. Responsive to receipt by one of the processing units of a packet subject to rate-limiting by a meter, an action to be taken on the packet is made with reference to a slave entry managed by the processing unit based on available credit of the slave entry. When the action indicates the packet is to be passed: (i) credits associated with passing the packet are deducted from the available credit; and (ii) the packet is passed to a subsequent stage of packet processing; otherwise, the packet is dropped.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: October 25, 2022
    Assignee: Fortinet, Inc.
    Inventors: Mengchen Yu, Guansong Zhang
  • Publication number: 20220103474
    Abstract: Systems and methods for network traffic metering credit distribution and packet processing in a network device having multiple processing units are provided. According to an embodiment, management of multiple meters is distributed among multiple processing units of a network device. Each meter is implemented in a form of a master entry and a slave entry. Responsive to receipt by one of the processing units of a packet subject to rate-limiting by a meter, an action to be taken on the packet is made with reference to a slave entry managed by the processing unit based on available credit of the slave entry. When the action indicates the packet is to be passed: (i) credits associated with passing the packet are deducted from the available credit; and (ii) the packet is passed to a subsequent stage of packet processing; otherwise, the packet is dropped.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 31, 2022
    Applicant: Fortinet, Inc.
    Inventors: Mengchen Yu, Guansong Zhang
  • Patent number: 6847985
    Abstract: An iterative mantissa calculator calculates a quotient mantissa for a divide mode or a result mantissa for a square-root mode. The calculator includes at least first and second summing devices. In the divide mode, each summing device calculates a respective estimated partial remainder W[j+1] for the next iteration, j+1, as 2*W[j]?Sj+1*D, where W[j] is the estimated partial remainder for the current iteration calculated during the prior iteration, Sj+1 is the quotient bit estimated for the next iteration, and D is the respective divisor bit. The estimated quotient bit for the next iteration is selected based on the calculated partial remainder. In the square-root mode, the first summing device calculates 2W[j]?2S[j]Sj+1, where W[j] is the estimated partial remainder and Sj+1 is the estimated result generated during the current iteration, j.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: January 25, 2005
    Assignee: LSI Logic Corporation
    Inventors: Gagan V. Gupta, Mengchen Yu