Patents by Inventor Meng-Han WANG

Meng-Han WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnect structures in integrated circuit chips
    Patent number: 12553939
    Abstract: An integrated circuit (IC) chip package and a method of fabricating the same are disclosed. The IC chip package includes a device layer on a first surface of a substrate, a first interconnect structure on the device layer, and a second interconnect structure on the second surface of the substrate. The first interconnect structure includes a fault detection line in a first metal line layer and configured to emit an electrical or an optical signal that is indicative of a presence or an absence of a defect in the device layer, a metal-free region on the fault detection line, and a metal line adjacent to the fault detection line in the first metal line layer. The fault detection line is electrically connected to the device layer.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: February 17, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Wang, Yu-Ting Lin, Chia Hong Lin, Kao Chih Liu, Wei-Cheng Liu
  • BACKSIDE INTERCONNECT STRUCTURES IN INTEGRATED CIRCUIT CHIPS
    Publication number: 20250357338
    Abstract: The present disclosure describes a structure that includes a substrate with first and second sides, a device layer disposed on the first side of the substrate, having a fault detection area on a back-side surface of the device layer configured to emit a signal that is indicative of a presence or an absence of a defect in the device layer, a first interconnect structure disposed on a front-side of the device layer, and a second interconnect structure disposed on the second side of the substrate, having a metal-free region aligned with the fault detection area and a first metal layer having first and second conductive lines disposed substantially parallel to each other. First and second sidewalls of the first and second conductive lines, respectively, facing each other are substantially aligned with first and second sides of the fault detection area.
    Type: Application
    Filed: August 4, 2025
    Publication date: November 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han WANG, Yu-Ting LIN, Chia Hong LIN, Wei-Cheng LIU
  • INTERCONNECT STRUCTURES IN INTEGRATED CIRCUIT CHIPS
    Publication number: 20250355041
    Abstract: An integrated circuit (IC) chip package and a method of fabricating the same are disclosed. The IC chip package includes a device layer on a first surface of a substrate, a first interconnect structure on the device layer, and a second interconnect structure on the second surface of the substrate. The first interconnect structure includes a fault detection line in a first metal line layer and configured to emit an electrical or an optical signal that is indicative of a presence or an absence of a defect in the device layer, a metal-free region on the fault detection line, and a metal line adjacent to the fault detection line in the first metal line layer. The fault detection line is electrically connected to the device layer.
    Type: Application
    Filed: July 30, 2025
    Publication date: November 20, 2025
    Applicant: Taiwan Serniconductor Manufacturing Company, Lid.
    Inventors: Meng-Han WANG, Yu-Ting LIN, Chia Hong LIN, Kao Chih LIU, Wei-Cheng LIU
  • INTERCONNECT STRUCTURES IN INTEGRATED CIRCUIT CHIPS
    Publication number: 20230160953
    Abstract: An integrated circuit (IC) chip package and a method of fabricating the same are disclosed. The IC chip package includes a device layer on a first surface of a substrate, a first interconnect structure on the device layer, and a second interconnect structure on the second surface of the substrate. The first interconnect structure includes a fault detection line in a first metal line layer and configured to emit an electrical or an optical signal that is indicative of a presence or an absence of a defect in the device layer, a metal-free region on the fault detection line, and a metal line adjacent to the fault detection line in the first metal line layer. The fault detection line is electrically connected to the device layer.
    Type: Application
    Filed: June 3, 2022
    Publication date: May 25, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han WANG, Yu-Ting LIN, Charlis LIN, Coach LIU, Wei-Cheng LIU
  • BACKSIDE INTERCONNECT STRUCTURES IN INTEGRATED CIRCUIT CHIPS
    Publication number: 20230046911
    Abstract: The present disclosure describes a structure that includes a substrate with first and second sides, a device layer disposed on the first side of the substrate, having a fault detection area on a back-side surface of the device layer configured to emit a signal that is indicative of a presence or an absence of a defect in the device layer, a first interconnect structure disposed on a front-side of the device layer, and a second interconnect structure disposed on the second side of the substrate, having a metal-free region aligned with the fault detection area and a first metal layer having first and second conductive lines disposed substantially parallel to each other. First and second sidewalls of the first and second conductive lines, respectively, facing each other are substantially aligned with first and second sides of the fault detection area.
    Type: Application
    Filed: June 29, 2022
    Publication date: February 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han WANG, Yu-Ting LIN, Chia Hong LIN, Wei-Cheng LIU