Patents by Inventor Meng-Jun Wang
Meng-Jun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11283007Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming an etch stop layer on the first IMD layer; forming a second IMD layer on the etch stop layer; forming a patterned hard mask on the second IMD layer; performing a first etching process to form a contact hole in the second IMD layer for exposing the etch stop layer; performing a second etching process to remove the patterned hard mask; performing a third etching process to remove the etch stop layer and the first IMD layer for exposing the MTJ; and forming a metal interconnection in the contact hole.Type: GrantFiled: October 7, 2020Date of Patent: March 22, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Kuo, Meng-Jun Wang, Yi-Wei Tseng, Yu-Tsung Lai, Jiunn-Hsiung Liao
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Publication number: 20210028352Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming an etch stop layer on the first IMD layer; forming a second IMD layer on the etch stop layer; forming a patterned hard mask on the second IMD layer; performing a first etching process to form a contact hole in the second IMD layer for exposing the etch stop layer; performing a second etching process to remove the patterned hard mask; performing a third etching process to remove the etch stop layer and the first IMD layer for exposing the MTJ; and forming a metal interconnection in the contact hole.Type: ApplicationFiled: October 7, 2020Publication date: January 28, 2021Inventors: Chih-Wei Kuo, Meng-Jun Wang, Yi-Wei Tseng, Yu-Tsung Lai, Jiunn-Hsiung Liao
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Publication number: 20200373479Abstract: A semiconductor device includes: a magnetic tunneling junction (MTJ) on a substrate; a first inter-metal dielectric (IMD) layer around the MTJ; a metal interconnection on and directly contacting the MTJ; a second IMD layer on the first IMD layer and around the metal interconnection; and a metal oxide layer on the second IMD layer and around the metal interconnection.Type: ApplicationFiled: June 13, 2019Publication date: November 26, 2020Inventors: Chih-Wei Kuo, Meng-Jun Wang, Yi-Wei Tseng, Yu-Tsung Lai, Jiunn-Hsiung Liao
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Patent number: 10847709Abstract: A semiconductor device includes: a magnetic tunneling junction (MTJ) on a substrate; a first inter-metal dielectric (IMD) layer around the MTJ; a metal interconnection on and directly contacting the MTJ; a second IMD layer on the first IMD layer and around the metal interconnection; and a metal oxide layer on the second IMD layer and around the metal interconnection.Type: GrantFiled: June 13, 2019Date of Patent: November 24, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Kuo, Meng-Jun Wang, Yi-Wei Tseng, Yu-Tsung Lai, Jiunn-Hsiung Liao
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Patent number: 10727397Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.Type: GrantFiled: January 29, 2019Date of Patent: July 28, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Yi-Wei Tseng, Meng-Jun Wang, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang, Yu-Ping Wang, Chien-Ting Lin, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, I-Ming Tseng
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Publication number: 20200227625Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.Type: ApplicationFiled: January 29, 2019Publication date: July 16, 2020Inventors: Hui-Lin Wang, Yi-Wei Tseng, Meng-Jun Wang, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang, Yu-Ping Wang, Chien-Ting Lin, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, I-Ming Tseng
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Patent number: 10636744Abstract: A memory device includes an insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, a connection hole disposed on the interconnection structure and penetrates the dielectric layer, an alignment mark trench penetrating the dielectric layer on a peripheral region, a first patterned conductive layer, and a patterned memory material layer. The first patterned conductive layer includes a connection structure at least partly disposed in the connection hole and a first pattern disposed in the alignment mark trench. The patterned memory material layer includes a first memory material pattern disposed on the connection structure and a second memory material pattern disposed in the alignment mark trench. Manufacturing yield and alignment condition of forming the memory device may be improved by disposing a part of the first patterned conductive layer in the alignment mark trench.Type: GrantFiled: August 9, 2018Date of Patent: April 28, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Meng-Jun Wang, Jiunn-Hsiung Liao, Yu-Tsung Lai
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Publication number: 20200051922Abstract: A memory device includes an insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, a connection hole disposed on the interconnection structure and penetrates the dielectric layer, an alignment mark trench penetrating the dielectric layer on a peripheral region, a first patterned conductive layer, and a patterned memory material layer. The first patterned conductive layer includes a connection structure at least partly disposed in the connection hole and a first pattern disposed in the alignment mark trench. The patterned memory material layer includes a first memory material pattern disposed on the connection structure and a second memory material pattern disposed in the alignment mark trench. Manufacturing yield and alignment condition of forming the memory device may be improved by disposing a part of the first patterned conductive layer in the alignment mark trench.Type: ApplicationFiled: August 9, 2018Publication date: February 13, 2020Inventors: Meng-Jun Wang, Jiunn-Hsiung Liao, Yu-Tsung Lai
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Patent number: 10438893Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a first metal interconnection and a second metal interconnection in the first IMD layer; removing part of the first IMD layer to form a recess between the first metal interconnection and the second metal interconnection; performing a curing process; and forming a second IMD layer on the first metal interconnection and the second metal interconnection.Type: GrantFiled: October 15, 2017Date of Patent: October 8, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hsien Chen, Meng-Jun Wang, Ting-Chun Wang, Chih-Sheng Chang
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Publication number: 20190096819Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a first metal interconnection and a second metal interconnection in the first IMD layer; removing part of the first IMD layer to form a recess between the first metal interconnection and the second metal interconnection; performing a curing process; and forming a second IMD layer on the first metal interconnection and the second metal interconnection.Type: ApplicationFiled: October 15, 2017Publication date: March 28, 2019Inventors: Shih-Hsien Chen, Meng-Jun Wang, Ting-Chun Wang, Chih-Sheng Chang
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Patent number: 9196491Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.Type: GrantFiled: October 22, 2013Date of Patent: November 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Te S. Lin, Meng Jun Wang, Ya Hui Chang, Hui Ouyang
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Publication number: 20140106479Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.Type: ApplicationFiled: October 22, 2013Publication date: April 17, 2014Inventors: Li-Te S. Lin, Meng Jun Wang, Ya Hui Chang, Hui Ouyang
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Patent number: 8563410Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.Type: GrantFiled: November 25, 2009Date of Patent: October 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Te S. Lin, Meng Jun Wang, Ya Hui Chang, Hui Ouyang
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Patent number: 8071487Abstract: A stacked structure for patterning a material layer to form an opening pattern with a predetermined opening width in the layer is provided. The stacked structure includes an underlayer, a silicon rich organic layer, and a photoresist layer. The underlayer is on the material layer. The silicon rich organic layer is between the underlayer and the photoresist layer. The thickness of the photoresist layer is smaller than that of the underlayer and larger than two times of the thickness of the silicon rich organic layer. The thickness of the underlayer is smaller than three times of the predetermined opening width.Type: GrantFiled: August 15, 2006Date of Patent: December 6, 2011Assignee: United Microelectronics Corp.Inventors: Meng-Jun Wang, Yi-Hsing Chen, Jiunn-Hsiung Liao, Min-Chieh Yang, Chuan-Kai Wang
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Publication number: 20110254142Abstract: A stacked structure for patterning a material layer to form an opening pattern with a predetermined opening width in the layer is provided. The stacked structure includes an underlayer, a silicon rich organic layer, and a photoresist layer. The underlayer is on the material layer. The silicon rich organic layer is between the underlayer and the photoresist layer. The thickness of the photoresist layer is smaller than that of the underlayer and larger than two times of the thickness of the silicon rich organic layer. The thickness of the underlayer is smaller than three times of the predetermined opening width.Type: ApplicationFiled: June 24, 2011Publication date: October 20, 2011Inventors: Meng-Jun Wang, Yi-Hsing Chen, Jiunn-Hsiung Liao, Min-Chieh Yang, Chuan-Kai Wang
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Publication number: 20110124134Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.Type: ApplicationFiled: November 25, 2009Publication date: May 26, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Te S. Lin, Meng Jun Wang, Ya Hui Chang, Hui Ouyang
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Patent number: 7592265Abstract: A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.Type: GrantFiled: January 4, 2007Date of Patent: September 22, 2009Assignee: United Microelectronics Corp.Inventors: Meng-Jun Wang, Yi-Hsing Chen, Min-Chieh Yang, Jiunn-Hsiung Liao
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Publication number: 20090206403Abstract: A stack structure for forming a gate of a MOS transistor includes a substrate including a plurality of shallow trench isolations therein; a dielectric layer, a conductive layer and a hard mask layer formed on the substrate in sequence; and a tri-layer stack comprising a top photo resist layer, a silicon-containing photo resist layer and a bottom anti-reflective coating (BARC) on the hard mask layer, wherein the silicon-containing photo resist layer comprises 10-30% silicon and the hard mask layer has a high etching selectivity ratio to the conductive layer.Type: ApplicationFiled: April 27, 2009Publication date: August 20, 2009Inventors: Meng-Jun Wang, Yi-Hsing Chen, Min-Chieh Yang, Jiunn-Hsiung Liao
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Publication number: 20080164526Abstract: A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.Type: ApplicationFiled: January 4, 2007Publication date: July 10, 2008Inventors: Meng-Jun Wang, Yi-Hsing Chen, Min-Chieh Yang, Jiunn-Hsiung Liao
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Publication number: 20080102643Abstract: A patterning method is provided. The method includes the steps of firstly forming an underlying layer, a silicon rich organic layer, and a photoresist layer on the material layer in succession. The photoresist layer is patterned, and the silicon rich organic layer is etched using the photoresist layer as a mask. Then, an etching process is performed to pattern the underlying layer using the silicon rich organic layer as a mask. Reactive gases adopted in the etching process include a passivation gas, an etching gas, and a carrier gas. The passivation gas forms a passivation layer at side walls of the patterned underlying layer during the etching process. After that, the material layer is etched using the underlying layer as a mask to form an opening in material layer. Finally, the underlying layer is removed.Type: ApplicationFiled: October 31, 2006Publication date: May 1, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Hsing Chen, Meng-Jun Wang, Jiunn-Hsiung Liao, Min-Chieh Yang