Abstract: A shift register, a gate driving circuit, and a driving method for a shift register. The shift register comprises: a cascade output sub-circuit, an output control sub-circuit, and a scanning output sub-circuit, wherein the cascade output sub-circuit is configured to provide a signal of a first power supply end or a second power supply end to a cascade output end under the control of signals of an input end, a first clock signal end, a second clock signal end, a first node, a second node and a third node; the output control sub-circuit is configured to provide the signal of the first node to a fourth node and the signal of the second node to a fifth node under the control of signals of the first node, the third node and a first control signal end to a third control signal end.

Abstract: A display substrate and a display device are provided. The display substrate includes: a base substrate, a plurality of data lines arranged on the base substrate, and a plurality of first sub-pixels arranged on the base substrate; the first sub-pixel includes: a first pixel opening, an orthographic projection of the first pixel opening on the base substrate partially overlaps an orthographic projection of a target data line among the plurality of data lines on the base substrate; a planarization compensation pattern, at least part of the planarization compensation pattern extends along a first direction, an orthographic projection of the planarization compensation pattern on the base substrate at least partially overlaps an orthographic projection of the first pixel opening on the base substrate, the planarization compensation pattern and the target data line are arranged along a second direction, and the second direction intersects the first direction.

Abstract: Provided is a display panel. The display panel has a display region, and includes: a base substrate; and a plurality of pixel circuits arrayed on a side of the base substrate, wherein the plurality of pixel circuits include a plurality of first pixel circuits and a plurality of dummy pixel circuits; a plurality of light-emitting devices on a side of the plurality of pixel circuits away from the base substrate, wherein the plurality of light-emitting devices are electrically connected to the plurality of first pixel circuits in one-to-one correspondence; and a plurality of data signal lines and a plurality of redundant signal lines that are disposed in the display region, wherein an extension direction of the plurality of data signal lines is coincident with an extension direction of the plurality of redundant signal lines.

Abstract: A display panel, a method for manufacturing the display panel, and a display device are provided. The display panel includes: a base substrate; at least one insulating layer arranged on the base substrate; an isolation pillar arranged on a side of the insulating layer distal to the base substrate, wherein a side surface of the isolation pillar is provided with an undercut structure; a light-emitting functional layer arranged on a side of the isolation pillar distal to the base substrate, wherein the light-emitting functional layer is disconnected at a position of the undercut structure; and an inorganic encapsulation layer arranged on a side of the light-emitting functional layer distal to the base substrate: wherein a first insulating layer in the at least one insulating layer is located in a first region where the isolation pillar is located.

Abstract: A display substrate and a display device are provided. The display substrate includes a first display area and a second display area. The first display area includes first light-emitting units and first pixel circuits, and the first pixel circuits are electrically connected with the first light-emitting units; the second display area includes second light-emitting units and second pixel circuits, and the second pixel circuits are electrically connected with the second light-emitting units; the first light-emitting units are electrically connected with first pixel circuits through first connection traces; the first display area includes a first region and a second region, the first region is located between the second region and the second display area, and a line width of at least one first connection trace located in the second region is smaller than a line width of at least one first connection trace located in the first region.

Abstract: A display substrate includes conductive layers including data lines, connection lines and fan-out lines. A connection line crosses at least one data line and is insulated from the crossed data line(s). A first fan-out line is electrically connected to the connection line, and a second fan-out line is electrically connected to an end of a second data line proximate to a fan-out region. The first fan-out line includes a transfer line. The fan-out region includes a first fan-out region and a second fan-out region, and the transfer line is located in the second fan-out region. The transfer line and second fan-out lines are located in different conductive layers, and crosses at least one second fan-out line. The transfer line includes a main body and two connection ends, and the main body is located on a side of the two connection ends proximate to the display region.

Abstract: A display panel, a driving method, and a display device. The display panel includes: a base substrate, subpixels, driving lines, data lines, a gate driving circuit including clock signal lines and shift register units arranged in extension direction of clock signal lines. The clock signal lines is divided into clock signal line groups; the shift register units is divided into register unit groups; the shift register units in same register unit group are cascaded, adjacent two of shift register units in the extension direction are in different register unit groups; one register unit group corresponds to one clock signal line group; the gate of an input transistor is connected to a clock signal line in a corresponding clock signal line group, the second pole of input transistor is connected to the gate of an output transistor; the second pole of output transistor is connected to at least one driving line.

Abstract: A display substrate includes a plurality of circuit units, wherein a circuit unit includes a pixel drive circuit, and the pixel drive circuit at least includes a plurality of transistors. In a plane perpendicular to the display substrate, the circuit unit includes a semiconductor layer disposed on a substrate, the semiconductor layer at least includes a first active pattern and a second active pattern, the first active pattern includes an active layer of at least one transistor, the second active pattern includes an active layer of at least one transistor.

Abstract: Provided is a display panel. The display panel includes: a base substrate having a display region and a peripheral region surrounding the display region; a plurality of pixel units disposed in the display region and including a light-emitting unit; a barrier structure disposed in the peripheral region and surrounding the plurality of pixel units; a connecting structure disposed in the peripheral region; a first insulating layer disposed between the first electrode layer and the base substrate, wherein a via hole is formed in a portion of the first insulating layer in the peripheral region; a circuit structure disposed in the peripheral region and including a first circuit structure; a second insulating layer disposed on a side of the second metal layer; and a third insulating layer disposed on a side of the second insulating layer and including a body pattern.

Abstract: A display substrate including a base substrate, a bottom metal layer (10) and a gate drive circuit. The base substrate includes a display region (AA), and a peripheral region (BB) located at a periphery of the display region (AA). A bottom metal layer (10) and a gate drive circuit are located in the peripheral region (BB), and the bottom metal layer (10) is electrically connected with at least one kind of signal lines. The gate drive circuit is located on one side of the bottom metal layer (10) away from the base substrate. The gate drive circuit includes a plurality of first circuit units. An orthographic projection of the bottom metal layer (10) on the base substrate is at least partially overlapped with an orthographic projection of at least one first circuit unit on the base substrate.

Abstract: Disclosed is a display substrate including a display region (100) and a bonding region (200) located on a side of the display region (100). The display region (100) includes a base substrate (101) and a drive circuit layer disposed on the base substrate (101). The drive circuit layer includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines (60), and a plurality of data connection lines (70). The data connection lines (70) include a first connection line (71) extending along a first direction and a second connection line (72) extending along a second direction. The first connection line (71) is electrically connected with the second connection line (72) and a data signal line (60) respectively. The first connection line (71) and the second connection line (72) are located in different conductive layers.

Abstract: Embodiments of the present disclosure provide a display substrate and a display apparatus. The display substrate has a display region and a peripheral region around the display region. The display substrate includes a substrate, a first voltage signal transmission structure and a light-emitting device layer that are arranged in sequence. The light-emitting device layer includes an anode layer and a cathode layer, and the anode layer is closer to the substrate than the cathode layer. The first voltage signal transmission structure is configured to transmit a first voltage signal to the cathode layer. The first voltage signal transmission structure includes a first portion located in the display region and a second portion located in the peripheral region, and the first portion is electrically connected to the second portion.

Abstract: A display panel includes a base substrate, data lines, first signal lines, second lines, first interconnection portions and a pixel electrode layer. One of the first interconnection portions is connected between a first dummy line and a second dummy line, and an orthographic projection of the first dummy line on the base substrate interests an orthographic projection of the second dummy line on the base substrate. Orthographic projections of the electrode portions on the base substrate do not overlap with orthographic projections of the first interconnection portions on the base substrate.

Abstract: A display substrate, a manufacturing method therefor, and a display device are disclosed. The display substrate includes multiple circuit units constituting multiple unit rows and multiple unit columns, multiple data signal lines and multiple data connection lines, the data connection lines include first connection lines extending along a first direction and second connection lines extending along a second direction, and the first connection lines are connected to the second connection lines; and in at least one circuit unit, the first connection lines are connected to the data signal lines through first connection holes, and at least one data signal line is provided between two first connection holes adjacent in the first direction.

Abstract: A display substrate and an electronic device are provided. The display substrate includes a base substrate, including a display region and a peripheral region on at least one side of the display region; and a shift register unit and a first clock signal line in the peripheral region of the base substrate, wherein the first clock signal line extends along a first direction on the base substrate, and is connected to a first clock signal terminal to be configured to provide a first clock signal to the shift register unit; the shift register unit includes an input circuit, an output circuit, a first control circuit, and an output control circuit; the output control circuit includes an output control transistor and a first capacitor, and the output circuit includes an output transistor and a second capacitor.

Abstract: This disclosure provides a display substrate, a display screen, and a display substrate driving method. The display substrate includes a first-category pixel row, a second-category pixel row, a first drive line, a second drive line and at least one category of data signal source; a first gate on array (GOA) circuit is used for providing a starting signal of a first frequency to the first-category pixel row; a second GOA circuit is used for providing a starting signal of a second frequency to the second-category pixel row; the at least one category of data signal source is used for supplying a data signal to data signal lines of the first-category pixel row and the second-category pixel row.

Abstract: A display substrate, a preparing method therefor, and a display apparatus are disclosed. The display substrate includes multiple data signal lines (60) and multiple data fanout lines (70) disposed along a first direction (X). A data signal line (60) extends in a second direction (Y). A first terminal of the data fanout line (70) is connected to a lead line (90). A second terminal of the data fanout line (70) is connected to the data signal line (60). At least one data fanout line (70) includes multiple fanout step sub-lines connected sequentially, the at least one fanout step sub-line at least includes a first fanout line (71) and a second fanout line (72) connected to each other. The first fanout line (71) has a line shape extending along a first direction (X) and the second fanout line (72) has a line shape extending along a second direction (Y).

Abstract: Disclosed are a display substrate and a display device. The display substrate includes: a base substrate, a first gate layer, a second gate layer and a first conductive layer. The first gate layer includes a reset signal line extending in a first direction, and a first electrode block; the second gate layer includes a second electrode block, wherein the second electrode block is configured to form a storage capacitor with the first electrode block; and the first conductive layer includes a power line extending in a second direction, wherein the reset signal line and the power line have a first overlapped region, and the second electrode block and the power line have a second overlapped region. The width of the power line located in the first overlapped region is smaller than the width of the power line located in the second overlapped region.

Abstract: An array substrate includes a plurality of first reset signal lines configured to provide a plurality of first reset signals, a plurality of second reset signal lines configured to provide a plurality of second reset signals, a plurality of third reset signal lines, and a plurality of first connecting lines, and a plurality of pixel driving circuits configured to drive light emission in a plurality of subpixels. A respective second reset signal line is connected to one or more of the plurality of third reset signal lines. The respective third reset signal line is connected to source electrodes of second reset transistors in a column of subpixels. A drain electrode of the seventh transistor is connected to an N3 node. The N3 node is a node connected to a drain electrode of the driving transistor and a source electrode of the light emitting control transistor.

Abstract: An array substrate includes a substrate, a plurality of pixel circuits, a first wiring layer, a bridge line layer and a second wiring layer. The first wiring layer includes first to third initialization signal lines. Each row of pixel circuits is electrically connected to a first initialization signal line, a second initialization signal line and a third initialization signal line. The bridge line layer includes of columns of transfer blocks and first fanout lines. The second wiring layer includes connecting lines, data lines and second fanout lines. Each connecting line is electrically connected to one of the first to third initialization signal lines by a column of transfer blocks. The data lines include first data lines located in a display area, an end of each second fanout line extends to a fanout area; and a first fanout line is electrically connected to a first data line and a second fanout line.