Abstract: A drive control circuit includes an input circuit, a first output circuit and a first output control circuit. An input circuit is configured to control the potentials of a first node and a second node under the control of a signal input terminal and a clock signal terminal. The first output circuit is configured to provide a first power supply signal to a third node under the control of a first node or to provide a second power supply signal to a first output terminal under the control of a second node. The first output control circuit is configured to turn on or turn off the third node and the first output terminal under the control of the first control terminal.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit and a voltage control circuit; the driving signal generation circuit generates an Nth stage of driving signal, the output control circuit connects the first control node and the second node under the control of the potential of the first node; the gating circuit controls to write a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to a potential of the first node; the output circuit connects the output driving terminal and the first voltage terminal under the control of the potential of the second node, and connects the output driving terminal and the second voltage terminal under the control of the potential of the third control node.

Abstract: Provided are a circuit and method for measuring capacitance and capacitance-voltage characteristics of a microelectronic device. The circuit includes a pulse generation sub-circuit, a sub-circuit P, and a sub-circuit N. The pulse generation sub-circuit generates clock pulses CLK1 and CLK2 with non-overlapping active levels. The sub-circuit P includes a first current mirror, a first large capacitor, a first transmission gate, a second transmission gate, a first OR gate, a first AND gate, a first NOT gate, a second NOT gate, and a third NOT gate. The sub-circuit N includes a second current mirror, a second large capacitor, a third transmission gate, a fourth transmission gate, a second OR gate, a second AND gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, and a seventh NOT gate.

Abstract: An array substrate is provided. The array substrate includes a voltage supply network. The voltage supply network includes, in a corner region of a peripheral area, a first peripheral voltage supply line; a plurality of second peripheral voltage supply lines; and an electrical connecting structure configured to connect the plurality of second peripheral voltage supply lines with the first peripheral voltage supply line. The electrical connecting structure crosses over at least one of the plurality of second peripheral voltage supply lines.

Abstract: Provided is a display panel. The display panel includes: a base substrate having a display region and a peripheral region surrounding the display region; a plurality of pixel units disposed in the display region and including a light-emitting unit; a barrier structure disposed in the peripheral region and surrounding the plurality of pixel units; a connecting structure disposed in the peripheral region; a first insulating layer disposed between the first electrode layer and the base substrate, wherein a via hole is formed in a portion of the first insulating layer in the peripheral region; a circuit structure disposed in the peripheral region and including a first circuit structure; a second insulating layer disposed on a side of the second metal layer; and a third insulating layer disposed on a side of the second insulating layer and including a body pattern.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit and an output circuit; the driving signal generation circuit generates and outputs the Nth stage of driving signal; the gating circuit controls to write the gating input signal into the first node; the output control circuit performs a NAND operation on the Nth stage of driving signal and the potential of the second terminal of the output control circuit to obtain a first output signal; the output circuit inverts the first output signal to obtain and provide an output driving signal through the output driving terminal; N is a positive integer.

Abstract: The present disclosure provides a driving circuitry, a driving method, a driving module, and a display device. The driving circuitry includes a driving signal generation circuitry, a gating circuitry, an output control circuitry and an output circuitry. The driving signal generation circuitry is configured to perform a shifting operation on an (N?1)th-level driving signal to obtain an Nth-level driving signal. The gating circuitry is configured to write a gating input signal into a first node under the control of a gating control signal. The output control circuitry is configured to perform an NAND operation on the Nth-level driving signal and a potential at a second end of the output control circuitry to obtain a first output signal. The output circuitry is configured to perform phase inversion on the first output signal to obtain and provide an output driving signal through an output driving end, where N is a positive integer.

Abstract: When sharing a picture with another user or device, an intelligent terminal like a mobile phone or a tablet computer may generate one or more photo bubbles based on image content in the to-be-shared picture. The bubbles carry information associated with the image content of the picture. The associated information is, for example, an introduction to the image content, another picture or video or news information that includes the image content, source information of the picture, a travel scheme generated based on a geographical location in the picture and a location in which an electronic device is located, and picture-related information entered by a user.

Abstract: An array substrate is provided. The array substrate includes a plurality of light emitting elements and a plurality of pixel driving circuits configured to drive light emission in the plurality of light emitting elements. In a first region, transistors of multiple pixel driving circuits of the plurality of pixel driving circuits are present, and the plurality of light emitting elements are absent. In a second region, multiple light emitting elements of the plurality of light emitting elements are present, and transistors of the plurality of pixel driving circuits are absent.

Abstract: Provided are a display panel, a manufacturing method, and a display device. The display panel includes: a substrate including a display area and a peripheral area; a driving circuit layer including: a pixel circuit in the display area, and a gate driver circuit on a side of the pixel circuit in proximity to the peripheral area, and at least partially in the display area; a first metal layer on a side of the driving circuit layer away from the substrate, insulated from the driving circuit layer; and a first electrode layer in the display area and on a side of the first metal layer away from the substrate, insulated from the first metal layer, and electrically connected to the pixel circuit; where orthographic projections, on the substrate, of the first electrode layer, the first metal layer, and the gate driver circuit, are at least partially overlapped.

Abstract: A display substrate and a display apparatus. The display substrate comprises a display region (100); the display region (100) comprises a base (101), a driving circuit layer (102) and a light-emitting structure layer (103); the driving circuit layer (102) comprises a plurality of circuit units, data signal lines (60), data connecting lines (70), low-voltage power supply lines (80), and power supply traces (90); the light-emitting structure layer (103) comprises a plurality of light-emitting devices; the circuit units comprise pixel driving circuits; the data signal lines (60) are configured to provide data signals for the pixel driving circuits; the low-voltage power supply lines (80) are configured to continuously provide low power supply voltage signals for the light-emitting devices; the data connecting lines (70) are connected to the data signal lines (60); and the power supply traces (90) are connected to the low-voltage power supply lines (80).

Abstract: Disclosed are a display substrate and a drive method therefor, and a display apparatus. The display substrate comprises a plurality of circuit units, a plurality of data signal lines and a plurality of data connection lines, wherein the data connection lines comprise a first connection line and a second connection line; at least one circuit unit comprises a data connection electrode; at least one circuit unit comprises a fan-out connection electrode; the second connection line is connected to the first connection line by means of the fan-out connection electrode; the first connection line is connected to the data signal lines by means of the data connection electrode; there is a first distance between the data connection electrode and the first connection line; there is a second distance between the fan-out connection electrode and the first connection line; and the first distance and the second distance are greater than 0.

Abstract: A display substrate includes conductive layers including data lines, connection lines and fan-out lines. A connection line crosses at least one data line and is insulated from the crossed data line(s). A first fan-out line is electrically connected to the connection line, and a second fan-out line is electrically connected to an end of a second data line proximate to a fan-out region. The first fan-out line includes a transfer line. The fan-out region includes a first fan-out region and a second fan-out region, and the transfer line is located in the second fan-out region. The transfer line and second fan-out lines are located in different conductive layers, and crosses at least one second fan-out line. The transfer line includes a main body and two connection ends, and the main body is located on a side of the two connection ends proximate to the display region.

Abstract: An array substrate is provided. The array substrate includes K number of columns of first pads. A respective first pad is connected to an anode of a light emitting element, a second electrode of a fifth transistor, and a second electrode of a sixth transistor. The K number of columns of first pads include a plurality of first-first pads in (2k-1)-th columns of the K columns and a plurality of second-first pads in (2k)-th columns of the K columns. A respective first-first pad and a respective second-first pad have different average line widths.

Abstract: A display panel, a method of manufacturing the display panel and a display device are provided in the present disclosure. The display panel includes: a substrate, a functional film layer arranged on the substrate, a first bending region capable of being bent along a first direction, a second bending region capable of being bent along a second direction, and a third bending region located between the first bending region and the second bending region. The first direction intersects the second direction. The functional film layer includes a non-hollowed region located in at least one of the first bending region and the second bending region, and a part of the functional film layer located in the third bending region includes a plurality of functional via holes spaced from each other.

Abstract: A display substrate and a display device are provided. In the display substrate, the plurality anodes includes a first anode, a second anode, a third anode, and a fourth anode, the second planarization layer includes a first via hole, a second via hole, a third via hole and a fourth via hole, the first via hole is located between the first virtual straight line and a second virtual straight line passing through a center of the effective light emitting region of the light emitting element corresponding to the first anode and extending along the first direction, the first via hole is located at a side of a bisector line, extending along a second direction, of the effective light emitting region of the light emitting element corresponding to the first anode, the second direction intersects with the first direction.

Abstract: Disclosed are a display substrate and a display device. In the display substrate, a first power voltage lead is configured to provide a first power voltage and located in the frame region; the first power voltage lead includes a lower lead extending along a portion of the lower edge corresponding to the first edge display region, but does not extend along a portion of the lower edge corresponding to the first middle display region; a first power voltage line includes an edge voltage line located in the first edge display region and a middle voltage line located in the first middle display region; the edge voltage line is directly connected with the lower lead to provide a first power voltage to sub-pixels located in the first edge display region, and the middle voltage line is spaced apart from the lower lead.

Abstract: Embodiments of the present disclosure provide a display substrate and a display apparatus. The display substrate has a display region and a peripheral region around the display region. The display substrate includes a substrate, a first voltage signal transmission structure and a light-emitting device layer that are arranged in sequence. The light-emitting device layer includes an anode layer and a cathode layer, and the anode layer is closer to the substrate than the cathode layer. The first voltage signal transmission structure is configured to transmit a first voltage signal to the cathode layer. The first voltage signal transmission structure includes a first portion located in the display region and a second portion located in the peripheral region, and the first portion is electrically connected to the second portion.

Abstract: A method and an apparatus for sorting and identifying single cells. The method includes a liquid supplying step, first nozzle imaging and recognizing step, single cell printing and imaging step, and second nozzle imaging step. The present disclosure adopts a high-throughput microfluidic design of thermal bubble printing chip and image recognition, which can expel the single cells gently and efficiently, thereby obtaining a high volume of single cells with high single cell yield and high single cell activity quickly. The method recognizes single cells based on cellular morphological features, facilitating obtaining single cells with high activity. Furthermore, the method provides the appearance of single cells on day zero, an important criterion for single cell analysis. The apparatus of the present disclosure provides a comprehensive solution for cellular experiments by monitoring the cell growth and locating the target cells based on fluorescent markers after single cell sorting.

Abstract: A display panel and a display device are disclosed. The display panel includes display area and a peripheral area surrounding the display area. The peripheral area includes a first peripheral area located at a side of the display area, the first peripheral area has a cell test area for arranging a cell test unit, the display panel has a first edge, and the first edge is located at a side of the first peripheral area away from the display area. The display panel is provided with a reference power bus and a touch signal line, and in the first peripheral area, the reference power bus has a reference power bus protrusion.