Abstract: A displaying base board includes an active area and a peripheral region, the peripheral region includes at least a first blocking part and a second blocking part; the peripheral region further includes a first power-supply signal line, and an orthographic projection of the first power-supply signal line on a substrate of the displaying base board has an overlapping part with individually an orthographic projection of the first blocking part on the substrate and an orthographic projection of the second blocking part on the substrate; and the first power-supply signal line is provided with a plurality of openings, and a region enclosed by orthographic projections on the substrate of outer contours of some of the openings falls within a region of the orthographic projection on the substrate of at least one of the first blocking part and the second blocking part.

Abstract: The present disclosure provides a driving circuitry, a driving method, a driving module, and a display device. The driving circuitry includes a driving signal generation circuitry, a gating circuitry, an output control circuitry and an output circuitry. The driving signal generation circuitry is configured to perform a shifting operation on an (N?1)th-level driving signal to obtain an Nth-level driving signal. The gating circuitry is configured to write a gating input signal into a first node under the control of a gating control signal. The output control circuitry is configured to perform an NAND operation on the Nth-level driving signal and a potential at a second end of the output control circuitry to obtain a first output signal. The output circuitry is configured to perform phase inversion on the first output signal to obtain and provide an output driving signal through an output driving end, where N is a positive integer.

Abstract: A display substrate has a fan-out area and includes a plurality of conductive layers. The plurality of conductive layers include data lines, connection lines and fan-out lines. A connection line is electrically connected to a first data line, and crosses at least one data line and is insulated from the crossed data line. A first fan-out line is electrically connected to the connection line. A second fan-out line is electrically connected to a second data line. The first fan-out line includes a transfer line, and is located in a different conductive layer from second fan-out lines and crosses at least one second fan-out line. An order of arrangement of ends of the fan-out lines away from the display area in a first direction is same as an order of arrangement of the data lines in the first direction.

Abstract: This disclosure provides a display substrate, a display, and a display substrate driving method. The display substrate includes a first-category pixel row, a second-category pixel row, a first drive line, a second drive line and at least one category of data signal source; a first gate on array (GOA) circuit is used for providing a starting signal of a first frequency to the first-category pixel row; a second GOA circuit is used for providing a starting signal of a second frequency to the second-category pixel row; the at least one category of data signal source is used for supplying a data signal to data signal lines of the first-category pixel row and the second-category pixel row.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a second node control circuit; the driving signal generation circuit generates an Nth stage of driving signal; the output control circuit controls to connect the first control node and the second node under the control of the potential of the first node; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to the potential of the first node; the second node control circuit controls to connect the second node and the first voltage terminal under the control of the potential of the first node.

Abstract: A shift register includes a shift module configured for causing the cascade signal output end to output a cascade signal in response to a signal of the input signal end; an reverse output module configured for causing the reverse signal output end to output a signal reverse to the cascade signal output end in response to a signal of the cascade signal output end; a latch module configured for causing an output end of the latch module to output a control signal of the masking signal end in response to signals of the cascade signal output end and the reverse signal output end of a previous level; and a selection output module configured for providing a signal of the first power supply end or the second power supply end to the driving signal output end in response to a signal of the output end of the latch module.

Abstract: A drive control circuit includes an input circuit, a first output circuit and a first output control circuit. An input circuit is configured to control the potentials of a first node and a second node under the control of a signal input terminal and a clock signal terminal. The first output circuit is configured to provide a first power supply signal to a third node under the control of a first node or to provide a second power supply signal to a first output terminal under the control of a second node. The first output control circuit is configured to turn on or turn off the third node and the first output terminal under the control of the first control terminal.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit and a voltage control circuit; the driving signal generation circuit generates an Nth stage of driving signal, the output control circuit connects the first control node and the second node under the control of the potential of the first node; the gating circuit controls to write a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to a potential of the first node; the output circuit connects the output driving terminal and the first voltage terminal under the control of the potential of the second node, and connects the output driving terminal and the second voltage terminal under the control of the potential of the third control node.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit and an output circuit; the driving signal generation circuit generates and outputs the Nth stage of driving signal; the gating circuit controls to write the gating input signal into the first node; the output control circuit performs a NAND operation on the Nth stage of driving signal and the potential of the second terminal of the output control circuit to obtain a first output signal; the output circuit inverts the first output signal to obtain and provide an output driving signal through the output driving terminal; N is a positive integer.

Abstract: The present disclosure provides a driving circuitry, a driving method, a driving module, and a display device. The driving circuitry includes a driving signal generation circuitry, a gating circuitry, an output control circuitry and an output circuitry. The driving signal generation circuitry is configured to perform a shifting operation on an (N?1)th-level driving signal to obtain an Nth-level driving signal. The gating circuitry is configured to write a gating input signal into a first node under the control of a gating control signal. The output control circuitry is configured to perform an NAND operation on the Nth-level driving signal and a potential at a second end of the output control circuitry to obtain a first output signal. The output circuitry is configured to perform phase inversion on the first output signal to obtain and provide an output driving signal through an output driving end, where N is a positive integer.

Abstract: An array substrate is provided. The array substrate includes a plurality of light emitting elements and a plurality of pixel driving circuits configured to drive light emission in the plurality of light emitting elements. In a first region, transistors of multiple pixel driving circuits of the plurality of pixel driving circuits are present, and the plurality of light emitting elements are absent. In a second region, multiple light emitting elements of the plurality of light emitting elements are present, and transistors of the plurality of pixel driving circuits are absent.

Abstract: A display substrate and a display apparatus. The display substrate comprises a display region (100); the display region (100) comprises a base (101), a driving circuit layer (102) and a light-emitting structure layer (103); the driving circuit layer (102) comprises a plurality of circuit units, data signal lines (60), data connecting lines (70), low-voltage power supply lines (80), and power supply traces (90); the light-emitting structure layer (103) comprises a plurality of light-emitting devices; the circuit units comprise pixel driving circuits; the data signal lines (60) are configured to provide data signals for the pixel driving circuits; the low-voltage power supply lines (80) are configured to continuously provide low power supply voltage signals for the light-emitting devices; the data connecting lines (70) are connected to the data signal lines (60); and the power supply traces (90) are connected to the low-voltage power supply lines (80).

Abstract: Disclosed are a display substrate and a drive method therefor, and a display apparatus. The display substrate comprises a plurality of circuit units, a plurality of data signal lines and a plurality of data connection lines, wherein the data connection lines comprise a first connection line and a second connection line; at least one circuit unit comprises a data connection electrode; at least one circuit unit comprises a fan-out connection electrode; the second connection line is connected to the first connection line by means of the fan-out connection electrode; the first connection line is connected to the data signal lines by means of the data connection electrode; there is a first distance between the data connection electrode and the first connection line; there is a second distance between the fan-out connection electrode and the first connection line; and the first distance and the second distance are greater than 0.

Abstract: A display substrate includes conductive layers including data lines, connection lines and fan-out lines. A connection line crosses at least one data line and is insulated from the crossed data line(s). A first fan-out line is electrically connected to the connection line, and a second fan-out line is electrically connected to an end of a second data line proximate to a fan-out region. The first fan-out line includes a transfer line. The fan-out region includes a first fan-out region and a second fan-out region, and the transfer line is located in the second fan-out region. The transfer line and second fan-out lines are located in different conductive layers, and crosses at least one second fan-out line. The transfer line includes a main body and two connection ends, and the main body is located on a side of the two connection ends proximate to the display region.

Abstract: A method for numerical reconstruction and heat transfer characteristics evaluation of a microstructure of thermal barrier coatings containing microcracks includes the following steps: determining a simulation area and size settings, generating random microcracks with different morphological characteristics and placing the microcracks in the simulation area, and determining whether a space occupied by the microcracks reaches a porosity ratio of the preset microcracks, building a general pore model of thermal barrier coatings (TBCs) based on the QSGS method, reconstructing true mesoscopic morphologies of the TBCs, determining whether the preset volume fraction has been reached, and building a heat transfer analysis model based on the thermal Lattice Boltzmann method to calculate heat insulation performance parameters such as temperature distribution, and thermal conductivity.

Abstract: A method for numerical reconstruction and heat transfer characteristics evaluation of a microstructure of thermal barrier coatings containing microcracks includes the following steps: determining a simulation area and size settings, generating random microcracks with different morphological characteristics and placing the microcracks in the simulation area, and determining whether a space occupied by the microcracks reaches a porosity ratio of the preset microcracks, building a general pore model of thermal barrier coatings (TBCs) based on the QSGS method, reconstructing true mesoscopic morphologies of the TBCs, determining whether the preset volume fraction has been reached, and building a heat transfer analysis model based on the thermal 1,attice Boltzmann method to calculate heat insulation performance parameters such as temperature distribution, and thermal conductivity.

Abstract: The present invention is directed to an in-house space antistatic & static electricity leakage method, comprising that multilayer different antistatic materials coated onto walls, ceilings, ground and glass doors, or windows so as to achieve the automatic compensation of antistatic action, wherein wall, ceiling and ground each is composed of base layer, interlayer and top layer. Said base layer is filled up using filling material containing antistatic material, scraped smooth, and compacted for 1-3 times; the interlayer can be coated with a thickness of 0.3-2 mm with antistatic interlayer material having decorative effect for 1-3 times. The top layer is coated 0.1-0.4 mm thick with antistatic covering material for 2-3 times. The glass door or window is coated with a thickness of 0.1-0.3 mm with transparent antistatic material for 2-8 times.