Abstract: A fabrication method of a silicon nanoneedle array with ultra-high aspect ratio includes the following steps: spin-coating two photoresist layers of methyl methacrylate (MMA) and polymethyl methacrylate (PMMA) A2 on a silicon substrate; subjecting the silicon substrate coated with the two photoresist layers of MMA and PMMA A2 to electron beam lithography to form a photoresist pattern on the silicon substrate; subjecting the silicon substrate on which the photoresist pattern is formed to electron beam evaporation (EBE) to deposit an Al film layer on the silicon substrate; subjecting the silicon substrate on which the Al film layer is deposited to stripping to obtain an Al film array deposited on the silicon substrate, which provides a mask for the subsequent inductively coupled plasma (ICP) etching process; and subjecting the silicon substrate covered with the Al mask to ICP silicon etching to obtain a silicon nanoneedle array structure.

Abstract: The present invention provides an improved SRAM memory cell based on a DICE structure, which comprises following structures: four inverter structures formed through arranging PMOS transistors and NMOS transistors in series, wherein the part between the drains of a PMOS transistor and an NMOS transistor serves as a storage node; each storage node controls the gate voltage of an NMOS transistor of the other inverter structure and of a PMOS transistor of another inverter structure; a transmission structure consisting of four NMOS transistors, whose source, gate and drain are respectively connected with a bit line/bit bar line, a word line and a storage node.

Abstract: The present invention provides an improved SRAM memory cell based on a DICE structure, which comprises following structures: four inverter structures formed through arranging PMOS transistors and NMOS transistors in series, wherein the part between the drains of a PMOS transistor and an NMOS transistor serves as a storage node; each storage node controls the gate voltage of an NMOS transistor of the other inverter structure and of a PMOS transistor of another inverter structure; a transmission structure consisting of four NMOS transistors, whose source, gate and drain are respectively connected with a bit line/bit bar line, a word line and a storage node.