Patents by Inventor Mengzhu QIAO

Mengzhu QIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12051615
    Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, an isolation trench being formed on the substrate; a silicon-rich isolation layer is formed in the isolation trench, the silicon-rich isolation layer covering an inner surface of the isolation trench; and an isolation oxide layer is formed in the isolation trench. The isolation oxide layer fills up the isolation trench.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: July 30, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Mengzhu Qiao
  • Patent number: 11877441
    Abstract: The present application provides a memory and a memory fabricating method. The memory includes a substrate, on which is disposed a separation layer, in which are arranged plural bitlines spaced apart from one another, the plural bitlines are arranged along a first direction, and each bitline is S-shaped. The method of fabricating the memory comprises the following steps: providing a substrate; forming on the substrate plural bitline grooves; forming in each bitline groove a first separation layer; forming bitlines on the first separation layer; forming a second separation layer on the bitlines; removing the substrate between adjacent separation walls, the separation wall including the first separation layer, the bitlines, and the second separation layer; and forming a third separation layer in a space between the adjacent separation walls, the third separation layer, the second separation layer, and the first separation layer together forming a separation layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Mengzhu Qiao, Tao Chen
  • Publication number: 20230024253
    Abstract: A semiconductor device includes a semiconductor substrate and word line structures. A plurality of active areas are formed in the substrate, and the plurality of active areas are isolated by an isolation structure. The isolation structure includes first areas and second areas. A dimension of the second areas is larger than that of the first areas in first direction. The word line structures are below a surface of the substrate and extend in first direction. The word line structures penetrate the isolation structure and the plurality of active areas. A word line structure includes first sub-word line structures located in first areas and second sub-word line structures located in second areas. The first sub-word line structures have first dimension in second direction, and the second sub-word line structures have second dimension at least larger than first dimension in second direction. The second direction forms an included angle with first direction.
    Type: Application
    Filed: September 29, 2022
    Publication date: January 26, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Mengzhu QIAO
  • Publication number: 20230010227
    Abstract: Provided are a shallow trench isolation structure and a method for manufacturing the same. The shallow trench isolation structure includes a substrate, a first isolation structure, a second isolation structure and a third isolation structure. The substrate includes a first trench. The first isolation layer is located in the first trench and provided with a second trench. The second isolation layer is located in the second trench and provided with a third trench. The third isolation layer fills the third trench. The second trench is a V-shaped trench, and a bottom surface of the second isolation layer is a V-shaped surface that is adapted to a shape of the second trench.
    Type: Application
    Filed: November 3, 2021
    Publication date: January 12, 2023
    Inventor: Mengzhu QIAO
  • Publication number: 20220285363
    Abstract: The present application provides a memory and a memory fabricating method. The memory includes a substrate, on which is disposed a separation layer, in which are arranged plural bitlines spaced apart from one another, the plural bitlines are arranged along a first direction, and each bitline is S-shaped. The method of fabricating the memory comprises the following steps: providing a substrate; forming on the substrate plural bitline grooves; forming in each bitline groove a first separation layer; forming bitlines on the first separation layer; forming a second separation layer on the bitlines; removing the substrate between adjacent separation walls, the separation wall including the first separation layer, the bitlines, and the second separation layer; and forming a third separation layer in a space between the adjacent separation walls, the third separation layer, the second separation layer, and the first separation layer together forming a separation layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: September 8, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Mengzhu QIAO, Tao CHEN
  • Publication number: 20220093451
    Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, an isolation trench being formed on the substrate; a silicon-rich isolation layer is formed in the isolation trench, the silicon-rich isolation layer covering an inner surface of the isolation trench; and an isolation oxide layer is formed in the isolation trench. The isolation oxide layer fills up the isolation trench.
    Type: Application
    Filed: August 18, 2021
    Publication date: March 24, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Mengzhu QIAO