Abstract: A memory cell arrangement is provided that may include: a plurality of first control lines; a plurality of second control lines; a plurality of third control lines; each of a plurality of memory cell sets includes memory cells and is assigned to a corresponding one of the plurality of first control lines and includes at least a first memory cell subset addressable via the corresponding first control line, a corresponding one of the plurality of second control lines, and the plurality of third control lines, and at least a second memory cell subset addressable via the corresponding first control line, the plurality of second control lines, and a corresponding one of the plurality of third control lines. The corresponding one of the plurality of third control lines addresses the second memory cell subset of each memory cell set of the plurality of memory cell sets.

Abstract: A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of a respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein the respective electrode layer and a respective electrode portion of the plurality of electrode portions form a first electrode and a second electrode of a capacitor and wherein at least one memory material portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion.

Abstract: According to various aspects, a memory cell arrangement includes: a first control line and a second control line; a plurality of memory structures disposed between the first control line and the second control line, wherein each memory structure of the plurality of memory structures comprises a third control line, a first memory cell and a second memory cell; wherein, for each memory structure of the plurality of memory structures, the first memory cell and the second memory cell are coupled to each other by the third control line; wherein, for each memory structure of the plurality of memory structures, the first memory cell is coupled to the first control line and the second memory cell is coupled to the second control line.

Abstract: A memory cell arrangement is provided that may include: a plurality of first control lines; a plurality of second control lines; a plurality of third control lines; each of a plurality of memory cell sets includes memory cells and is assigned to a corresponding one of the plurality of first control lines and includes at least a first memory cell subset addressable via the corresponding first control line, a corresponding one of the plurality of second control lines, and the plurality of third control lines, and at least a second memory cell subset addressable via the corresponding first control line, the plurality of second control lines, and a corresponding one of the plurality of third control lines. The corresponding one of the plurality of third control lines addresses the second memory cell subset of each memory cell set of the plurality of memory cell sets.

Abstract: A memory cell arrangement is provided that may include: a plurality of first control lines; a plurality of second control lines; a plurality of third control lines; each of a plurality of memory cell sets includes memory cells and is assigned to a corresponding one of the plurality of first control lines and includes at least a first memory cell subset addressable via the corresponding first control line, a corresponding one of the plurality of second control lines, and the plurality of third control lines, and at least a second memory cell subset addressable via the corresponding first control line, the plurality of second control lines, and a corresponding one of the plurality of third control lines. The corresponding one of the plurality of third control lines addresses the second memory cell subset of each memory cell set of the plurality of memory cell sets.

Abstract: A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of a respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein the respective electrode layer and a respective electrode portion of the plurality of electrode portions form a first electrode and a second electrode of a capacitor and wherein at least one memory material portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion.

Abstract: A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of the respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein at least one remanent-polarizable portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion.

Abstract: A memory cell arrangement is provided that may include: a plurality of first control lines; a plurality of second control lines; a plurality of third control lines; each of a plurality of memory cell sets includes memory cells and is assigned to a corresponding one of the plurality of first control lines and includes at least a first memory cell subset addressable via the corresponding first control line, a corresponding one of the plurality of second control lines, and the plurality of third control lines, and at least a second memory cell subset addressable via the corresponding first control line, the plurality of second control lines, and a corresponding one of the plurality of third control lines. The corresponding one of the plurality of third control lines addresses the second memory cell subset of each memory cell set of the plurality of memory cell sets.

Abstract: According to various aspects, a memory cell arrangement includes: a first control line and a second control line; a plurality of memory structures disposed between the first control line and the second control line, wherein each memory structure of the plurality of memory structures comprises a third control line, a first memory cell and a second memory cell; wherein, for each memory structure of the plurality of memory structures, the first memory cell and the second memory cell are coupled to each other by the third control line; wherein, for each memory structure of the plurality of memory structures, the first memory cell is coupled to the first control line and the second memory cell is coupled to the second control line.

Abstract: A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of the respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein at least one remanent-polarizable portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion.

Abstract: A device for transmitting and receiving is disclosed that includes: a) an antenna, b) a transmitting/receiving unit for transmitting and receiving data according to a communications standard, which has a transmitting unit, connected to the antenna, for transmitting first data frames to a second transmitting/receiving device and a receiving unit, connected to the antenna, for receiving second data frames from the second transmitting/receiving device, and c) a control unit, connected to the transmitting/receiving unit for controlling the transmitting/receiving unit, whereby the control unit is designed (c1) to instruct the transmitting/receiving unit to transmit a first data frame and (c2) to receive the second data frame from the transmitting/receiving unit.

Abstract: A WLAN (Wireless Local Area Network) receiver is provided that provides at least two acquisition units and at least two tracking units. The acquisition units perform a synchronization acquisition process, and the tracking units perform a synchronization tracking process. The acquisition units are arranged for being operated sequentially while the tracking units are arranged for being operated simultaneously. In an embodiment, frequency and phase error correction may be performed separately, and those units that operate at higher sampling rates may be located before lower-rate units. The synchronization process may include data-aided as well as non data-aided algorithms.

Abstract: A device for transmitting and receiving is disclosed that includes: a) an antenna, b) a transmitting/receiving unit for transmitting and receiving data according to a communications standard, which has a transmitting unit, connected to the antenna, for transmitting first data frames to a second transmitting/receiving device and a receiving unit, connected to the antenna, for receiving second data frames from the second transmitting/receiving device, and c) a control unit, connected to the transmitting/receiving unit for controlling the transmitting/receiving unit, whereby the control unit is designed (c1) to instruct the transmitting/receiving unit to transmit a first data frame and (c2) to receive the second data frame from the transmitting/receiving unit.

Abstract: A phase error correction technique in receivers such as WLAN receivers is provided. Such receivers comprise a phase error correction unit connected to receive an input signal having a phase error and adapted to generate an output signal having a corrected phase error. Further, the receiver comprises a despreader which is adapted to despread a data signal. The despreader is connected to the phase error correction unit to provide the despread data signal to the phase error correction unit. The phase error correction unit is arranged for correcting the phase error dependent on the despread data signal. The despreader may be a Barker matched filter or a CCK matched filter, and there may be provided a multiplexer for selecting one of the filters.

Abstract: An average tracking mechanism for a data communication receiver is provided. The average tracking mechanism of the receiver is connected to receive an input stream of data samples and is adapted to keep track of an average over a predefined number of most recently received data samples. The average tracking mechanism comprises a calculation unit that is adapted to calculate an approximate value of the average and a storage unit for storing calculated approximate values. The calculation unit is adapted to calculate the approximate value by retrieving a previously calculated approximate value from the storage unit and calculating a weighted sum of the retrieved approximate value and a current data sample. The average approximation technique may be used in a comb filter of a preamble detector in a WLAN receiver.

Abstract: A phase error correction technique in data communication receivers such as WLAN (Wireless Local Area Network) receivers is provided. A signal having a phase error is received, and a phase error correction mechanism having a loop structure is operated on the input signal to correct the phase error. The corrected signal still has a residual phase error. The residual phase error is then compensated taking into account a loop time delay of the loop structure. Further, a phase change rate may be taken into account, and a smoothing process may additionally be performed.

Abstract: An error correction technique for data communication receivers such as WLAN (Wireless Local Area Network) receivers is provided. The error correction technique is for correcting a frequency and/or phase error in an incoming digitally modulated signal. A constellation manipulator is provided that is adapted to manipulate the phase constellation system of the incoming digitally modulated system by mapping each constellation point of the phase constellation system to a predefined range of phase angles. The predefined range has a width of less than 2?. Further, an error detector is provided that is connected to receive data from the constellation manipulator. The data pertains to the manipulated phase constellation system. The error detector is adapted to evaluate the data to detect the frequency and/or phase error.

Abstract: A phase error corrector circuit and method are disclosed. In one embodiment, a phase error corrector circuit delays a PSK modulated signal and multiplies the delayed PSK modulated signal by the PSK modulated signal in order to generate a forward phase correction signal. The input signal is then mixed with the forward phase correction signal. In another embodiment, a phase error corrector circuit calculates a forward phase offset of a complex PSK modulated signal. The complex PSK modulated signal is phase shifted in a mixer by a phase difference offset in order to generate a phase corrected signal. A backward phase correction means calculates a backward phase offset based on the phase corrected signal. A subtractor subtracts the forward phase offset from the backward phase offset for outputting a difference phase offset to the mixer.

Abstract: A WLAN (Wireless Local Area Network) receiver having a synchronization unit is provided. The synchronization unit comprises a first functional unit for performing a first signal processing function, a second functional unit for performing a second signal processing function different from the first signal processing function, and at least one signal processing circuit. In the synchronization unit the first functional unit is operating at least one of the signal processing circuits for performing the first signal processing function, and the second functional unit is arranged for operating the at least one signal processing circuit operated by the first functional unit for performing the second signal processing function. Since the above-described signal processing circuits or modules can be re-used for the antenna diversity unit and the preamble detection unit this results in a smaller number of gates and an improved density of the circuitry.

Abstract: A data communications device and method is provided that apply an LMS (Least Mean Square) channel estimation. A coefficient calculation unit generates a signal that represents at least one channel coefficient that is indicative of a property of the channel such as its finite impulse response. Further, an error calculation unit generates an error signal. Dependent on the error signal, the channel coefficients are updated by performing the LMS algorithm using a step size of two to a negative integer power. This allows for a simple, less complex implementation, and may be applied in a wireless local area network receiver for adjusting filter coefficients.