Abstract: The invention relates to a circuit for frequency synthesis, comprising: a digital controlled oscillator, comprising (a) a clock generator; an accumulator circuit to which the signal from the clock generator is fed; and a control digit feed circuit for feeding to the digital oscillator a signal representing a control digit; and (b) a phase-locked loop which is connected to the carry output terminal of the accumulator circuit and which is provided with a phase detector, a low-pass filter and a controlled oscillator, wherein the carry output terminal is connected to the phase detector. The digital controlled oscillator is preferable adapted to generate a signal representing a remainder, wherein a correction circuit is arranged for deriving a correction signal from the remainder. The correction circuit is connected to a combination circuit connected to one of the inputs of the phase detector or to a combination circuit incorporated in the phase-locked loop. The circuits can also be connected in cascade.

Abstract: A digital phase locked loop for recovering a stable clock signal from at least one input signal subject to jitter is disclosed. The loop included a digital input circuit receiving at least one input signal, a digital controlled oscillator for generating an output signal at a desired frequency and a control signal representing the time error in the output signal, a stable local oscillator for providing clock signals to the digital controlled oscillator, and a tapped delay line for receiving the output signal of the digital controlled oscillator. The tapped delay line comprises a plurality of buffers each introducing a delay of less than one clock cycle of the digital controlled oscillator. The tapped delay line produces an output signal from a tap determined by the control signal. A digital phase comparator receives at least one input signal from the input circuit and the output signal from the tapped delay line to generate a digital input signal controlling the digital controlled oscillator.