Abstract: A quantum dot structure is described wherein the quantum dot structure comprises one or more semiconductor layers arranged on a substrate; an array comprising a plurality of quantum dot regions (104), the plurality of quantum dot regions being formed in the one or more semiconductor layers, the quantum dot regions being separated by barrier regions (106, 108), wherein first barrier electrodes (110) are arranged in one direction over the quantum dot regions (104) and second barrier electrodes (112) are arranged in a second direction over the quantum dot regions (104), in such a way that in operation quantum dots are defined in the quantum dot regions (104) by the potential barriers induced by the first and second barrier electrodes (110, 112); the first barrier electrodes (110) and second barrier electrodes (112) crossing each other at the barrier regions (108), so that each barrier region (108) is coupled to one of the first barrier electrodes (110) and to one of the second barrier electrodes (112).

Abstract: An integrated quantum dot structure comprises: one or more semiconductor layers arranged on a substrate; a single electron tunneling (SET) transistor formed in or over the one or more semiconductor layers, the SET transistor comprising a source and a drain connected by tunneling junctions to a conductive island; a plurality of quantum dot regions, preferably an array, arranged around the SET transistor, the plurality of quantum dot regions being formed in the one or more semiconductor layers and the SET transistor being configured to readout change states of the plurality of quantum dot regions; one or more insulating layers provided over the SET transistor and the quantum dot regions; a source electrode and a drain electrode arranged over the one or more insulating layers; and, first and second nano-scale metallic vias connecting the source and drain of the SET transistor to the source and drain electrodes respectively.

Abstract: A method of controlling random charge effects originating from local defects (202-1, 202-2, 202-3) above a quantum dot in a quantum dot array is described, wherein the method comprises: selecting one or more electrodes (Vg, Vb) configured to control one or more quantum structures formed in one or more semiconductor layers arranged on a substrate; and, applying one or more first voltage pulses (inset) to the one or more selected electrodes, the amplitude of the one or more first voltage pulses being selected to induce a shift in one or more charge states (210-1, 210-2, 210-3) of one or more offset charges in one or more dielectric, semiconductor and/or interface layers between the one or more selected electrodes (Vg, Vb) and the one or more semiconductor layers in which the one or more quantum dots are formed by the application of voltages on one or more electrodes (Vg, Vb).

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.

Abstract: The present disclosure provides a scalable architecture for an advanced processing apparatus for performing quantum processing. The architecture is based on an all-silicon CMOS fabrication technology. Transistor-based control circuits, together with floating gates, are used to operate a two-dimensional array of qubits. The qubits are defined by the spin states of a single electron confined in a quantum dot.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.

Abstract: The present disclosure provides a scalable architecture for an advanced processing apparatus for performing quantum processing. The architecture is based on an all-silicon CMOS fabrication technology. Transistor-based control circuits, together with floating gates, are used to operate a two-dimensional array of qubits. The qubits are defined by the spin states of a single electron confined in a quantum dot.

Abstract: A processing element for an advanced processing apparatus. The processing element comprises a silicon-insulator interface and a confining arrangement for confining one or more quantum dots in the semiconductor. The processing element has also a control arrangement for controlling a quantum property of the one or more quantum dots and operate the one or more quantum dots as a qubit to perform quantum processing.

Abstract: A processing element for an advanced processing apparatus. The processing element comprises a silicon-insulator interface and a confining arrangement for confining one or more quantum dots in the semiconductor. The processing element has also a control arrangement for controlling a quantum property of the one or more quantum dots and operate the one or more quantum dots as a qubit to perform quantum processing.