Abstract: An energy efficient Ethernet physical layer (PHY) device including an EEE control module configured to generate a control signal to transition the PHY device into a low power consumption mode based an operating condition, and a pause frame generator module responsive to the control signals to generate a pause frame. The pause frame generator module is configured to send the pause frame to a media access control (MAC) device to reduce an incoming flow of data packets from the MAC device to the PHY device for a pause time duration. In operation, the pause frame generator module generates the pause frame including a pause time indicating the length of time for the PHY device to be in the low power consumption mode. The value of the pause time for each pause frame is determined adaptively based on the type of data traffic to be transmitted from the PHY device.

Abstract: An energy efficient Ethernet physical layer (PHY) device including an EEE control module configured to generate a control signal to transition the PHY device into a low power consumption mode based an operating condition, and a pause frame generator module responsive to the control signals to generate a pause frame. The pause frame generator module is configured to send the pause frame to a media access control (MAC) device to reduce an incoming flow of data packets from the MAC device to the PHY device for a pause time duration. In operation, the pause frame generator module generates the pause frame including a pause time indicating the length of time for the PHY device to be in the low power consumption mode. The value of the pause time for each pause frame is determined adaptively based on the type of data traffic to be transmitted from the PHY device.

Abstract: An energy efficient Ethernet physical layer (PHY) device including an EEE control module configured to generate a control signal to transition the PHY device into a low power consumption mode based an operating condition, and a pause frame generator module responsive to the control signals to generate a pause frame. The pause frame generator module is configured to send the pause frame to a media access control (MAC) device to reduce an incoming flow of data packets from the MAC device to the PHY device for a pause time duration. In operation, the pause frame generator module generates the pause frame including a pause time indicating the length of time for the PHY device to be in the low power consumption mode. The value of the pause time for each pause frame is determined adaptively based on the amount of data traffic to be transmitted from the PHY device.

Abstract: A network device includes a physical layer transceiver configured to receive incoming data on a data link at an input clock rate and to store the incoming data in a buffer. The physical layer transceiver includes a Media Independent Interface (MII) controller configured to receive the incoming data stored in the buffer and to transmit the incoming data over a MII bus based on a MII clock where the MII clock is a spread spectrum clock. The network device further includes a Media Access Control (MAC) device configured to receiving incoming data from the physical layer transceiver over the MII bus where the incoming data is clocked by the spread spectrum MII clock.

Abstract: A network device includes a physical layer transceiver configured to receive incoming data on a data link at an input clock rate and to store the incoming data in a buffer. The physical layer transceiver includes a Media Independent Interface (MII) controller configured to receive the incoming data stored in the buffer and to transmit the incoming data over a MII bus based on a MII clock where the MII clock is a spread spectrum clock. The network device further includes a Media Access Control (MAC) device configured to receiving incoming data from the physical layer transceiver over the MII bus where the incoming data is clocked by the spread spectrum MII clock.

Abstract: A device for Electro-Magnetic Interference (EMI) reduction in an Ethernet system has an Ethernet compatible device. The Ethernet compatible device has a filter for adjusting a signal outputted by the Ethernet compatible device for EMI reduction.

Abstract: An energy efficient Ethernet physical layer (PHY) device including an EEE control module configured to generate a control signal to transition the PHY device into a low power consumption mode based an operating condition, and a pause frame generator module responsive to the control signals to generate a pause frame. The pause frame generator module is configured to send the pause frame to a media access control (MAC) device to reduce an incoming flow of data packets from the MAC device to the PHY device for a pause time duration. In operation, the pause frame generator module generates the pause frame including a pause time indicating the length of time for the PHY device to be in the low power consumption mode. The value of the pause time for each pause frame is determined adaptively based on the amount of data traffic to be transmitted from the PHY device.

Abstract: A line driver includes current sources and resistors that form a bridge circuit in which a bridge resistor is connected between an internal node and ground, and a series resistor connected between the internal node and the driver's output node. The internal node is connected to receive a unit current from a first stage transistor, and the output node is connected to receive an amplified current from a second stage transistor that is N times the unit current. The bridge resistor is formed with a resistance value set such that the voltages at the internal node and the output node are equal, i.e., such that no current flows through the series resistor. The resistance value of the series resistor is thus adjustable to optimize output impedance in a manner independent of the driver's gain. An echo cancellation circuit is utilized to eliminate noise from two associated line drivers.

Abstract: A device for Electro-Magnetic Interference (EMI) reduction in an Ethernet system has an Ethernet compatible device. The Ethernet compatible device has a filter for adjusting a signal outputted by the Ethernet compatible device for EMI reduction.

Abstract: A line driver includes current sources and resistors that form a bridge circuit in which a bridge resistor is connected between an internal node and ground, and a series resistor connected between the internal node and the driver's output node. The internal node is connected to receive a unit current from a first stage transistor, and the output node is connected to receive an amplified current from a second stage transistor that is N times the unit current. The bridge resistor is formed with a resistance value set such that the voltages at the internal node and the output node are equal, i.e., such that no current flows through the series resistor. The resistance value of the series resistor is thus adjustable to optimize output impedance in a manner independent of the driver's gain. An echo cancellation circuit is utilized to eliminate noise from two associated line drivers.

Abstract: A semiconductor relay switch having two data ports receiving incoming signals and a power supply terminal receiving a power supply voltage is responsive to a power supply voltage level and an energy level of the incoming signals to open and close its conduction paths. The relay switch is open when a valid power supply level is detected and when there is no supply power on the power supply terminal but a high energy level is detected in the incoming signals. The relay switch is closed to allow conduction between the two data ports only when there is no power supply voltage on the power supply terminal and an energy level below a predetermined threshold is detected in the incoming signals. In one embodiment, the semiconductor relay switch includes a main conduction switch circuit, an energy detect circuit and a control signal generator.

Abstract: A line driver includes current sources and resistors that form a bridge circuit in which a bridge resistor is connected between an internal node and ground, and a series resistor connected between the internal node and the driver's output node. The internal node is connected to receive a unit current from a first stage transistor, and the output node is connected to receive an amplified current from a second stage transistor that is N times the unit current. The bridge resistor is formed with a resistance value set such that the voltages at the internal node and the output node are equal, i.e., such that no current flows through the series resistor. The resistance value of the series resistor is thus adjustable to optimize output impedance in a manner independent of the driver's gain. An echo cancellation circuit is utilized to eliminate noise from two associated line drivers.

Abstract: A semiconductor relay switch having two data ports receiving incoming signals and a power supply terminal receiving a power supply voltage is responsive to a power supply voltage level and an energy level of the incoming signals to open and close its conduction paths. The relay switch is open when a valid power supply level is detected and when there is no supply power on the power supply terminal but a high energy level is detected in the incoming signals. The relay switch is closed to allow conduction between the two data ports only when there is no power supply voltage on the power supply terminal and an energy level below a predetermined threshold is detected in the incoming signals. In one embodiment, the semiconductor relay switch includes a main conduction switch circuit, an energy detect circuit and a control signal generator.

Abstract: A semiconductor relay switch having two data ports receiving incoming signals and a power supply terminal receiving a power supply voltage is responsive to a power supply voltage level and an energy level of the incoming signals to open and close its conduction paths. The relay switch is open when a valid power supply level is detected and when there is no supply power on the power supply terminal but a high energy level is detected in the incoming signals. The relay switch is closed to allow conduction between the two data ports only when there is no power supply voltage on the power supply terminal and an energy level below a predetermined threshold is detected in the incoming signals. In one embodiment, the semiconductor relay switch includes a main conduction switch circuit, an energy detect circuit and a control signal generator.

Abstract: A semiconductor relay switch having two data ports receiving incoming signals and a power supply terminal receiving a power supply voltage is responsive to a power supply voltage level and an energy level of the incoming signals to open and close its conduction paths. The relay switch is open when a valid power supply level is detected and when there is no supply power on the power supply terminal but a high energy level is detected in the incoming signals. The relay switch is closed to allow conduction between the two data ports only when there is no power supply voltage on the power supply terminal and an energy level below a predetermined threshold is detected in the incoming signals. In one embodiment, the semiconductor relay switch includes a main conduction switch circuit, an energy detect circuit and a control signal generator.

Abstract: A clock generator and method generates a plurality of clocks of different frequencies using a delay lock loop and a sequencer. The delay lock loop receives an input clock signal having an input clock frequency and generates a plurality of delayed clock signals each having a frequency same as the input clock frequency and a different phase delay in relation to the input clock signal. The sequencer receives the delayed clock signals and selects one the delayed clock signals at any moment according to a predetermined sequence to generate an output clock signal having an output clock frequency corresponding to the predetermined sequence. The frequency of the output clock signal is controlled by the sequence in which the delayed clock signals are by the sequencer.

Abstract: A circuit for driving a communication line includes a transformer having a secondary winding for supplying an output drive signal, and having a primary winding connected to conduct current through a control element that receives a control signal which stabilizes the amplitude of output drive signal, independent of variations in supply voltage. A control circuit produces the control signal in response to the difference of signals produced across conductive elements that are connected to separate current sources which supply currents determined by arithmetic relationships between the values of different supply voltages.

Abstract: An output driver is provided with driving and filtering capability. An output current driver and output voltage driver embodiments are provided. The output current driver includes, an operational amplifier having a first input for receiving a first input voltage V1, a second input for receiving a second input voltage V2, and an output for generating an output voltage Vc. The output current driver also includes a transistor having an input terminal coupled to the output of the operational amplifier for receiving the output voltage Vc, a first terminal coupled to a differential pair, and a second terminal coupled to the second input of the operational amplifier, wherein an output current Iout flows across the transistor. A control current ICONTROL determines a value of the first input voltage V1, while the output voltage Vc controls the transistor so that the second voltage V2 becomes equal to the first voltage V1.

Abstract: An apparatus for tracking a peak level of an input signal includes a comparator for comparing the peak level of the input signal with a reference peak voltage signal. A sample and block circuit is coupled to the output of the comparator and is capable of sampling a portion of the input signal. The sampled portion of the input signal is defined by a smart window (timing window) which is received by the sample and block circuit. The sample and block circuit controls a charge pump that determines the level of the reference peak voltage signal. A method of generating a reference peak voltage signal includes receiving an input data, generating a timing window based upon the input data to define a sampling portion in the input data, comparing a level of the reference peak voltage signal with a level of the sampling portion in the input data, and determining a level of the reference peak voltage signal based upon the comparing step.

Abstract: An apparatus of compensating for offset in a received signal generated from a forward path stage, includes a first peak detector for receiving a first signal from the forward path stage and capable of detecting a peak of the first signal; a second peak detector for receiving a second signal from the forward path stage and capable of detecting a peak of the second signal; a differential amplifier coupled to the first peak detector and the second peak detector and capable of generating an offset control signal; and a compensation stage coupled to the differential amplifier and capable of compensating for offset in the received signal in response to the offset control signal.