Patents by Inventor Mentor Graphics Corporation

Mentor Graphics Corporation has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140052430
    Abstract: Embodiments of the disclosed technology are directed toward facilitating the concurrent emulation of multiple electronic designs in a single emulator without partition restrictions. In certain exemplary embodiments, an emulation environment comprising an emulator and an emulation control station is provided. The emulation control station includes a model compaction module that is configured to combine multiple design models into a combined model. In some implementations, the design models are merged to form the combined model, where each design model is represented as a virtual design with the combined model. Subsequently, the emulator can be configured to implement the combined model. Furthermore, an emulation clock control component is provided that allows for portions of the emulated combined model to be “stalled” during emulation without affecting other portions.
    Type: Application
    Filed: April 29, 2013
    Publication date: February 20, 2014
    Applicant: Mentor Graphics Corporation
    Inventor: Mentor Graphics Corporation
  • Publication number: 20140040850
    Abstract: Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice.
    Type: Application
    Filed: January 22, 2013
    Publication date: February 6, 2014
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventor: Mentor Graphics Corporation
  • Publication number: 20140032204
    Abstract: Technologies for debugging hardware errors discovered during hardware assisted software verification processes are provided. For example, in one embodiment, a concurrent emulation debug environment including a concurrent emulation system, an emulation trace module and a model state module is provided. The concurrent emulation system includes an emulator and an emulation control station configured to allow simultaneous emulation of multiple electronic designs. The model state module is configured to record the state of the electronic designs during emulation and the emulation trace module is configured to capture trace data associated with the emulation. A backup and capture module is also disclosed that is configured to store the recorded state and the captured trace data for use during a hardware debug process.
    Type: Application
    Filed: May 1, 2013
    Publication date: January 30, 2014
    Applicant: Mentor Graphics Corporation
    Inventor: Mentor Graphics Corporation
  • Publication number: 20140013290
    Abstract: Various implementations of the invention provide for the determination of a test set that satisfies a coverage model, where portions of the search space need not be searched in order to generate the test set. With various implementations of the invention, a search space defined by a set of inputs for an electronic design and a coverage model is identified. The search space is then fractured into subspaces. Subsequently, the subspaces are solved to determine if they include at least one input sequence that satisfies the coverage constraints defined in the coverage model. The subspaces found to include at least one input sequence that satisfies these coverage constraints, are then searched for unique input sequences in order to generate a test set. Subspaces found not to include at least one input sequence that satisfies the coverage constraints may be excluded from the overall search space.
    Type: Application
    Filed: February 1, 2013
    Publication date: January 9, 2014
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventor: MENTOR GRAPHICS CORPORATION
  • Publication number: 20130298102
    Abstract: Various embodiments provide for the determination of a test set that satisfies a coverage model, where portions of the search space need not be searched in order to generate the test set. With various embodiments, a search space defined by a set of inputs for an electronic design and a coverage model is identified. The search space is then fractured into subspaces. Subsequently, the subspaces are solved to determine if they include at least one input sequence that satisfies the coverage constraints defined in the coverage model. The subspaces found to include at least one input sequence that satisfies these coverage constraints, are then searched for unique input sequences in order to generate a test set. Subspaces found not to include at least one input sequence that satisfies the coverage constraints may be excluded from the overall search space.
    Type: Application
    Filed: May 1, 2013
    Publication date: November 7, 2013
    Applicant: Mentor Graphics Corporation
    Inventor: Mentor Graphics Corporation
  • Publication number: 20130275112
    Abstract: Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced.
    Type: Application
    Filed: December 31, 2012
    Publication date: October 17, 2013
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventor: Mentor Graphics Corporation
  • Publication number: 20130227500
    Abstract: A system for calculating mask data to create a desired layout pattern on a wafer reads all or a portion of a desired layout pattern. Mask data having pixels with transmission values is defined along with corresponding optimal mask data pixel transmission values. An objective function is defined that compares image intensities as would be generated on a wafer with an optimal image intensity at a point corresponding to a pixel. The objective function is minimized to determine the transmission values of the mask pixels that will reproduce the desired layout pattern on a wafer.
    Type: Application
    Filed: September 19, 2012
    Publication date: August 29, 2013
    Applicant: Mentor Graphics Corporation
    Inventor: Mentor Graphics Corporation
  • Publication number: 20130226531
    Abstract: A method of designing a wiring harness using a wiring harness design tool can include allowing a first user to access and edit a first wiring harness design component in a wiring harness design workspace, allowing a second user to access and edit a second wiring harness design component in the wiring harness design workspace at least during a portion of the time that the first user is allowed to access and edit the first wiring harness design component, and displaying the first and second wiring harness design components to the first and second users during at least a portion of the time that access is allowed to the first and second users.
    Type: Application
    Filed: February 19, 2013
    Publication date: August 29, 2013
    Applicant: Mentor Graphics Corporation
    Inventor: Mentor Graphics Corporation
  • Publication number: 20130219216
    Abstract: Aspects of the invention relate to techniques for classifying memory failure bitmaps using both rule-based classification and artificial neural network-based classification methods. The rule-based classification method employs classification rules comprising those for global failure patterns. The artificial neural network-based classification method classifies local failure patterns. One of the artificial neural network models is the Kohonen self-organizing map model. The input vector for a failure pattern may contain four elements: pattern aspect ratio, failing bit ratio, dominant failing column number and dominant failing row number.
    Type: Application
    Filed: February 15, 2013
    Publication date: August 22, 2013
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventor: MENTOR GRAPHICS CORPORATION
  • Publication number: 20130198700
    Abstract: Aspects of the invention relate to techniques for repairing layout design defects after layout data have been processed by resolution enhancement techniques. The repair process first determines a re-correction region that includes three portions: core, context and visible portions. An inverse lithography process is then performed on the core portion of the re-correction region while taking into account effects from the context portion of the re-correction region to generate a first modified re-correction region. A traditional OPC process is then performed on the core and context portions of the first modified re-correction region while taking into account effects from the visible portion of the first modified re-correction region to generate a second modified re-correction region.
    Type: Application
    Filed: January 14, 2013
    Publication date: August 1, 2013
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventor: Mentor Graphics Corporation
  • Publication number: 20130198709
    Abstract: Aspects of the invention provide for the maintenance of user modified portions of a map between a test bench and a test set generator during an iterative electronic design process. Various implementations of the invention provide for matching sections within a design for an electronic device with corresponding sections in a map between the elements in the design to elements in a graph representation of the design. The matched sections are then compared to determine if any discrepancies exists, such as, for example, if the design has been recently changed. If any discrepancies do exist, then it is determined whether the section of the map can be updated or must be replaced entirely to resolve the discrepancies. Various implementations of the invention provide that the process can be repeated during an iterative design flow such that as the design is modified during the iterative design flow, the map can be updated to reflect the changes.
    Type: Application
    Filed: January 31, 2013
    Publication date: August 1, 2013
    Applicant: Mentor Graphics Corporation
    Inventor: Mentor Graphics Corporation
  • Publication number: 20130198708
    Abstract: Aspects of the invention are directed towards placing components within a layout design for a PCB. More specifically, various implementations of the invention provide methods and apparatuses that can dynamically adjust the shape or placement of component groups during an HGP process. With some implementations of the invention, an HGP process for planning the layout of a PCB is provided. Furthermore, component groups, which conflict, geographically, with either another component group or some other object within the layout design are allowed to be placed during the planning process. Subsequently, the placement locations for one or both of the conflicting component groups are adjusted to resolve the conflict. In some implementations, the geometric boundary, or footprint, of one or both of the component groups is adjusted to resolve the conflict.
    Type: Application
    Filed: January 31, 2013
    Publication date: August 1, 2013
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventor: MENTOR GRAPHICS CORPORATION
  • Publication number: 20130191805
    Abstract: Aspects of the invention relate to simulation of circuits with repetitive elements. With various implementations of the invention, a circuit design for simulation is analyzed to derive information of memory-circuit device groups that comprise word-line-driven device groups. If the circuit design is hierarchically structured, the circuit design is flattened to the device level but keep the memory-circuit device groups intact. The circuit design is then partitioned into a plurality of subcircuits for simulation. During transient simulation, whether an instance of a word-line-driven device group is activated is first determined. If activated, whether device model values exist for the word-line-driven device group at a voltage state associated with the activated instance is then determined. If they exist, the device model values are associated with the activated instance. If they do not exist, the device model values are computed for, stored for and associated with the activated instance.
    Type: Application
    Filed: December 10, 2012
    Publication date: July 25, 2013
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventor: MENTOR GRAPHICS CORPORATION
  • Publication number: 20130191792
    Abstract: After layout design data has been modified using a resolution enhancement process, a repair flow is initiated. This repair flow includes checking a layout design altered by a resolution enhancement process for errors. A repair process is performed to correct detected sub-resolution assist feature errors. The repair process may employ a rule-based sub-resolution assist feature technique, a model-based sub-resolution assist feature technique, an inverse lithography-based sub-resolution assist feature technique, or any combination thereof.
    Type: Application
    Filed: January 9, 2013
    Publication date: July 25, 2013
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventor: MENTOR GRAPHICS CORPORATION
  • Publication number: 20130191795
    Abstract: Aspects of the invention relate to techniques for repairing layout design defects after layout data have been processed by resolution enhancement techniques. The repair process first determines a re-correction region that includes three portions: core, transition and visible portions. An inverse lithography process is then performed on the core and transition portions of the re-correction region while taking into account effects from the visible portion to generate a modified re-correction region. The transition portion is processed based on distance from boundary between the transition portion and the core portion such that layout features near the boundary between the transition portion and the core portion are adjusted more than layout features farther away from the boundary.
    Type: Application
    Filed: January 14, 2013
    Publication date: July 25, 2013
    Applicant: Mentor Graphics Corporation
    Inventor: Mentor Graphics Corporation
  • Publication number: 20130166976
    Abstract: Aspects of the invention relate to techniques for determining scan chains that could be diagnosed with high resolution. A circuit design and the information of scan cells for the circuit design are analyzed to determine information of potential logic relationship between the scan cells. The information of potential logic relationship between the scan cells may comprise information of fan-in cones for the scan cells. Based at least in part on the information of potential logic relationship between the scan cells, scan chains may be formed. The formation of scan chains may be further based on layout information of the circuit design. The formation of scan chains may be further based on compactor information of the circuit design.
    Type: Application
    Filed: November 29, 2012
    Publication date: June 27, 2013
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventor: Mentor Graphics Corporation
  • Publication number: 20130145213
    Abstract: Aspects of the invention relate to techniques for fault diagnosis based on dynamic circuit design partitioning. According to various implementations of the invention, a sub-circuit is extracted from a circuit design based on failure information of one or more integrated circuit devices. The extraction process may comprise combining fan-in cones of failing observation points included in the failure information. The extraction process may further comprise adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points. Clock information of test patterns and/or layout information of the circuit design may be extracted and used in the sub-circuit extraction process. The extracted sub-circuit may then be used for diagnosing the one or more integrated circuit devices.
    Type: Application
    Filed: November 19, 2012
    Publication date: June 6, 2013
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventor: Mentor Graphics Corporation
  • Publication number: 20130080849
    Abstract: Embodiments of the disclosed technology comprise techniques that can be used to generate scan chain test patterns and improve scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. At least some embodiments can be used to locate faults over multiple capture cycles in the scan chain.
    Type: Application
    Filed: November 19, 2012
    Publication date: March 28, 2013
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventor: MENTOR GRAPHICS CORPORATION
  • Publication number: 20130042213
    Abstract: Branching of the data-flow in a mask data preparation processes is described herein. In various implementations, the output stream from a first mask data processing operation is branched. Subsequently, the branched output stream may be connected to the input stream of a first independent mask data preparation operation and a second independent mask data preparation operation. This provides that the first and the second independent mask data preparation operations may operate in parallel. Furthermore, this provides that the first and the second independent mask data preparation operations may operate upon discrete “portions” of the data processed by the first mask data preparation operation.
    Type: Application
    Filed: October 15, 2012
    Publication date: February 14, 2013
    Applicant: Mentor Graphics Corporation
    Inventor: Mentor Graphics Corporation
  • Publication number: 20130036390
    Abstract: The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign.
    Type: Application
    Filed: October 11, 2012
    Publication date: February 7, 2013
    Applicant: Mentor Graphics Corporation
    Inventor: Mentor Graphics Corporation