Patents by Inventor Merav Sicron

Merav Sicron has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250110209
    Abstract: For example, a radar Radio Head (RH) may be configured to determine Range-Doppler (RD) information corresponding to a plurality of RD bins based on digital radar Receive (Rx) signals representing radar Radio Frequency (RF) Rx signals received by one or more Rx antennas; to detect one or more detected RD bins based on the RD information; to provide filtered RD information including RD information corresponding to the one or more detected RD bins and excluding RD information of one or more excluded RD bins, which are not included in the one or more detected RD bins; and to send the filtered RD information to another processor via a communication interconnect.
    Type: Application
    Filed: September 30, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Merav Sicron, Ofer Gueta, Kfir Mandel, Ophir Shabtay, Adi Panzer, Ziv Barak
  • Publication number: 20240338150
    Abstract: For example, a Data Mover and Transformer (DMT) may be configured to transform a first data array from a first memory into a second data array to be stored in a second memory. The DMT may include a Row to Column (R2C) transformer configured to transform a data sub-array into a transformed data sub-array by transforming one or more rows of the data sub-array into one or more respective columns of the transformed data sub-array; a memory reader to populate the data sub-array with data retrieved from the first memory according to a memory read pattern, wherein the memory read pattern is based on a predefined transformation from the first data array to the second data array; and a memory writer to write data from the transformed data sub-array to the second memory according to a memory write pattern, wherein the memory write pattern is based on the predefined transformation.
    Type: Application
    Filed: March 18, 2024
    Publication date: October 10, 2024
    Applicant: MobilEye Vision Technologies Ltd.
    Inventor: Merav Sicron
  • Publication number: 20240319332
    Abstract: For example, an apparatus may include a scheduler configured to determine scheduling information to schedule radar transmissions of a radar device during a sequence of radar frames. For example, the scheduler may be configured to determine a burst-based frame setting to schedule a sequence of radar burst transmissions during a radar frame of the sequence of radar frames. In one example, the burst-based frame setting may include a setting of a burst gap duration. In one example, the burst gap duration may include a duration of a burst gap between first and second consecutive radar burst transmissions of the sequence of radar burst transmissions.
    Type: Application
    Filed: June 29, 2022
    Publication date: September 26, 2024
    Applicant: Intel Corporation
    Inventors: Oren Shalita, Moshe Teplitsky, Sharon Heruti, Alon Cohen, Ophir Shabtay, Ilia Yoffe, Roy Sofer, Merav Sicron
  • Publication number: 20230266452
    Abstract: For example, a radar processor may include an input to receive radar Receive (Rx) information based on radar Rx signals received by a plurality of Radio Heads (RHs); and one or more Baseband (BB) Processing Units (BPUs) including a plurality of processing resources configured to generate radar information by processing the radar Rx information according to a plurality of BB-processing tasks. The one or more BPUs may be configured to allocate the plurality of processing resources to the plurality of RHs based on an RH to resource (RH-resource) allocation scheme. The RH-resource allocation scheme may be configured to define a plurality of RH-specific resource allocations for the plurality of RHs, respectively. For example, an RH-specific resource allocation for an RH may define a plurality of RH-allocated processing resources to perform the plurality of BB-processing tasks based on radar Rx information from the RH.
    Type: Application
    Filed: June 29, 2022
    Publication date: August 24, 2023
    Applicant: Intel Corporation
    Inventors: Merav Sicron, Sharon Heruti, Ofer Gueta, Ophir Shabtay
  • Patent number: 11599379
    Abstract: Methods and systems for a virtual machine environment are provided. One method includes allocating a memory for storing a dirty pages data structure for tracking writes to a virtual machine memory by an adapter coupled to a computing device and shared by a plurality of virtual machines; initiating a tracking operation by the adapter or a virtual function driver to track writes to the virtual memory; providing access to the dirty pages data structure in response to a query command, while the adapter or the virtual function driver tracks writes to the virtual machine memory; and providing a number of dirty pages within the dirty pages data structure and a pointer the dirty pages data structure by the adapter or the virtual function driver.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: March 7, 2023
    Assignee: MARVELL ASIA PTE, LTD
    Inventors: Merav Sicron, Rafi Shalom
  • Patent number: 10956202
    Abstract: Methods and systems for a virtual machine environment are provided. One method includes allocating a memory for storing a dirty pages data structure for tracking writes to a virtual machine memory by an adapter coupled to a computing device and shared by a plurality of virtual machines; initiating a tracking operation by the adapter or a virtual function driver to track writes to the virtual memory; providing access to the dirty pages data structure in response to a query command, while the adapter or the virtual function driver tracks writes to the virtual machine memory; and providing a number of dirty pages within the dirty pages data structure and a pointer the dirty pages data structure by the adapter or the virtual function driver.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: March 23, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Merav Sicron, Rafi Shalom
  • Patent number: 10592271
    Abstract: Methods and systems for a virtual machine environment are provided. One method includes allocating a memory for storing a dirty pages data structure for tracking writes to a virtual machine memory by an adapter coupled to a computing device and shared by a plurality of virtual machines; initiating a tracking operation by the adapter or a virtual function driver to track writes to the virtual memory; providing access to the dirty pages data structure in response to a query command, while the adapter or the virtual function driver tracks writes to the virtual machine memory; and providing a number of dirty pages within the dirty pages data structure and a pointer the dirty pages data structure by the adapter or the virtual function driver.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 17, 2020
    Assignee: Cavium, LLC
    Inventors: Merav Sicron, Rafi Shalom
  • Patent number: 8478907
    Abstract: A network interface device for use with a host computer that includes a host processor and a memory, and which is configured to concurrently run a master operating system and at least one virtual operating system. The device includes a bus interface that communicates over a bus with the host processor and the memory, and a network interface, which is coupled to send and receive data packets carrying data over a packet network. A protocol processor is coupled between the bus interface and the network interface so as to convey the data between the network interface and the memory while performing protocol processing on the data packets under instructions from the at least one virtual operating system, while bypassing the master operating system.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: July 2, 2013
    Assignee: Broadcom Corporation
    Inventors: Eliezer Aloni, Kobby Carmona, Shay Mizrachi, Rafi Shalom, Merav Sicron, Dov Hirshfeld, Amit Oren, Caitlin Bestler, Uri Tal, Uri Elzur, Kan (Frankie) Fan, Scott McDaniel
  • Patent number: 7835380
    Abstract: A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface, including at least first and second physical ports, which are coupled to send and receive data packets carrying data over a packet network. A protocol processor includes a single transmit processing pipeline and a single receive processing pipeline, which are coupled between the bus interface and the network interface so as to convey the data between both of the first and second physical ports of the network interface and the memory via the bus interface while performing protocol offload processing on the data packets.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: November 16, 2010
    Inventors: Eliezer Aloni, Kobby Carmona, Shay Mizrachi, Rafi Shalom, Merav Sicron, Dov Hirshfeld, Amit Oren, Caitlin Bestler, Uri Tal, Steven B. Lindsay, Kan (Frankie) Fan, Hav Khauv
  • Patent number: 7826470
    Abstract: A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface that sends and receive data packets carrying data over a packet network. A protocol processor conveys the data between the network interface and the memory via the bus interface while performing protocol offload processing on the data packets in accordance with multiple different application flows. The bus interface queues the data for transmission over the bus in a plurality of queues that are respectively assigned to the different application flows, and transmits the data over the bus according to the queues.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: November 2, 2010
    Inventors: Eliezer Aloni, Kobby Carmona, Shay Mizrachi, Rafi Shalom, Merav Sicron, Dov Hirshfeld, Amit Oren, Caitlin Bestler, Uri Tal
  • Patent number: 7688838
    Abstract: A method for communication includes inputting from a host processor to a network interface device a sequence of work requests indicative of operations to be carried out by the network interface device with respect to a plurality of the connections. The device looks ahead through the sequence in order to identify at least first and second operations that are to be carried out with respect to one of the connections in response to first and second work requests, respectively, wherein the second work request does not immediately follow the first work request in the sequence. The device loads the context data for the one of the connections from a host memory into a context cache, and performs at least the first and second operations sequentially while the context data are held in the cache.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: March 30, 2010
    Inventors: Eliezer Aloni, Kobby Carmona, Shay Mizrachi, Rafi Shalom, Caitlin Bestler, Merav Sicron, Dov Hirshfeld, Amit Oren, Uri Tal
  • Publication number: 20080155154
    Abstract: Certain aspects of a method and system for coalescing task completions may include coalescing a plurality of completions per connection associated with an I/O request. An event may be communicated to a global event queue, and an entry may be posted to the global event queue for a particular connection based on the coalesced plurality of completions. At least one central processing unit (CPU) may be interrupted based on the coalesced plurality of completions.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 26, 2008
    Inventors: Yuval Kenan, Merav Sicron, Eliezer Aloni
  • Publication number: 20080155571
    Abstract: Certain aspects of a method and system for host software concurrent processing of a network connection using multiple central processing units (CPUs) may be disclosed. Exemplary aspects of the method may include a network system comprising a plurality of processors and a NIC. After completion of one or more received I/O requests, a plurality of completions may be distributed among two or more of the plurality of CPUs. The plurality of CPUs may be enabled to handle processing for one or more network connections and each network connection may be associated with a plurality of completion queues. Each CPU may be associated with at least one global event queue.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 26, 2008
    Inventors: Yuval Kenan, Merav Sicron, Eliezer Aloni