Abstract: A test system for testing a capacitive-sense touchscreen is disclosed. Specifically, the test system may be incorporated within a controller that is also used to control operations of the touchscreen. The controller may include an Integrated Circuit and the test system may correspond to a test capacitor embedded into the Integrated Circuit.

Abstract: A test system for testing a capacitive-sense touchscreen is disclosed. Specifically, the test system may be incorporated within a controller that is also used to control operations of the touchscreen. The controller may include an Integrated Circuit and the test system may correspond to a test capacitor embedded into the Integrated Circuit.

Abstract: A method and structure for the handling and discarding of packets in a packet data network. The method includes a packet data network receiving one or more packets from one or more remote locations and initiating a transfer of a packet of the one or more packets to a remote destination. The remote destination is operable to act as a destination port of a switch. The transfer of the packet is initiated while the packet of the one or more packets is being received, and the packet validity is also checked while the transfer of the packet is initiated. If the packet is invalid, the transfer of the packet of the one or more packets to the remote destination is canceled. Determining packet validity includes inspection of a packet header. The structure has a receive link determining packet validity and passing this error signal to a packet processor. The packet processor has a packet transfer request generator, a packet checker, packet reader, packet memory and tag memory.

Abstract: In general, a system and method for providing data packet flow control is disclosed. Generally, a switch is provided that contains a series of ports, an arbiter and a hub. The arbiter determines an outgoing port, wherein the outgoing port is one port for the series of ports, for transmission of a data packet received by the switch, determines whether the outgoing port is available to receive the received data packet, and regulates transmission of the received data packet to a destination end node. The hub provides a point-to-point connection between any two of the series of ports and the arbiter.

Abstract: A fast with-in range comparator is implemented in digital logic. A packet arrives at a device for processing. Initial packet data that is available in a first read cycle, is used to compute data that is necessary for later cycles. The initial data and the subsequently data are then used to test a single value against a range of values. In a method of the present invention a range is separated into two ranges. An upper limit of the first range is tested to determine whether the value is below the upper limit. If this test fails, the value is tested to determine whether the value is between the upper limit of the first range and the upper limit of the full range. The ranges are tested by constructing a bit vector. Data representing the capability of a communicating port, is then used to index into the bit vector. The outcome of the index is a value that signifies whether the port can support the packet or not.

Abstract: A switch for use with an InfiniBand network. The switch includes a hub that redirects packets from a first InfiniBand device to a second InfiniBand device, a buffer that receives packets from the first InfiniBand device, and plurality of ports for transferring the data to the hub. A plurality of registers are coupled to the buffer for storing data from the packets. A switch network for selectively connecting the registers to the ports such that each register transfers a different portion of the data to a selected port.

Abstract: An architecture and method for dynamically allocating and deallocating memory for variable length packets with a variable number of virtual lanes in an Infiniband subnetwork. This architecture uses linked lists and tags to handle the variable number of Virtual Lanes and the variable packet sizes. The memory allocation scheme is independent of Virtual Lane allocation and the maximum Virtual Lane depth. The disclosed architecture is also able to process Infiniband packet data comprising variable packet lengths, a fixed memory allocation size, and deallocation of memory when packets are either multicast or unicast. The memory allocation scheme uses linked lists to perform memory allocation and deallocation, while tags are used to track Infiniband subnetwork and switch-specific issues. Memory allocation and deallocation is performed using several data and pointer tables. These tables store packet data information, packet buffer address information, and pointer data and point addresses.

Abstract: An architecture and method for dynamically allocating and deallocating memory for variable length packets with a variable number of virtual lanes in an Infiniband subnetwork. This architecture uses linked lists and tags to handle the variable number of virtual Lanes and the variable packet sizes. The memory allocation scheme is independent of Virtual Lane allocation and the maximum Virtual Lane depth. The disclosed architecture is also able to process Infiniband packet data comprising variable packet lengths, a fixed memory allocation size, and deallocation of memory when packets are either multicast or unicast. The memory allocation scheme uses linked lists to perform memory allocation and deallocation, while tags are used to track Infiniband subnetwork and switch-specific issues. Memory allocation and deallocation is performed using several data and pointer tables. These tables store packet data information, packet buffer address information, and pointer data and point addresses.

Abstract: A method and structure for the handling and discarding of packets in a packet data network. The method includes a packet data network receiving one or more packets from one or more remote locations and initiating a transfer of a packet of the one or more packets to a remote destination. The remote destination is operable to act as a destination port of a switch. The transfer of the packet is initiated while the packet of the one or more packets is being received, and the packet validity is also checked while the transfer of the packet is initiated. If the packet is invalid, the transfer of the packet of the one or more packets to the remote destination is canceled. Determining packet validity includes inspection of a packet header. The structure has a receive link determining packet validity and passing this error signal to a packet processor. The packet processor has a packet transfer request generator, a packet checker, packet reader, packet memory and tag memory.

Abstract: In general, a system and method for providing data packet flow control is disclosed. Generally, a switch is provided that contains a series of ports, an arbiter and a hub. The arbiter determines an outgoing port, wherein the outgoing port is one port for the series of ports, for transmission of a data packet received by the switch, determines whether the outgoing port is available to receive the received data packet, and regulates transmission of the received data packet to a destination end node. The hub provides a point-to-point connection between any two of the series of ports and the arbiter.

Abstract: A switch for use with an InfiniBand network. The switch includes a crossbar that redirects packet based data based on a forwarding table. At least one port that receives data from a network and selectively transfers that data to the crossbar at 1×, 4×, and 12× speeds. A state machine that controls the changing of the speed of operation of the port.

Abstract: A switch for use with an InfiniBand network. The switch includes a hub that redirects packets from a first InfiniBand device to a second InfiniBand device, a buffer that receives packets from the first InfiniBand device, and plurality of ports for transferring the data to the hub. A plurality of registers are coupled to the buffer for storing data from the packets. A switch network for selectively connecting the registers to the ports such that each register transfers a different portion of the data to a selected port.

Abstract: A fast with-in range comparator is implemented in digital logic. A packet arrives at a device for processing. Initial packet data that is available in a first read cycle, is used to compute data that is necessary for later cycles. The initial data and the subsequently data are then used to test a single value against a range of values. In a method of the present invention a range is separated into two ranges. An upper limit of the first range is tested to determine whether the value is below the upper limit. If this test fails, the value is tested to determine whether the value is between the upper limit of the first range and the upper limit of the full range. The ranges are tested by constructing a bit vector. Data representing the capability of a communicating port, is then used to index into the bit vector. The outcome of the index is a value that signifies whether the port can support the packet or not.

Abstract: The present invention is a method for accessing a user defined custom routine through a graphical interface of an application program. The method comprises the steps of: (a) linking the user defined custom routine to the application program; (b) displaying a means for accessing the user defined custom routine on a graphical interface; and (c) transferring control to the user defined custom routine when a user activates the means.

Abstract: A system comprises a flag interface module, a flag query having a selectable value based on a user authorization level, a query communicator, and a flag value communicator for communicating a new flag value from the flag interface module to a test program in response to the query communicator that enables a user to modify an execution sequence [e.g., modifying the flow] of the test program executing on a computer controlling a testing system. The execution sequence of the test program is modified only if the user has a proper authorization level. The execution sequence is modified by an authorized user without requiring the test program to be recompiled.

Abstract: The present invention is a method for specifying test flow and binning of an integrated circuit part in an integrated circuit tester. The method comprises the steps of receiving descriptions of the tests, receiving test flow statements indicating when the tests are to be executed, receiving binning statements, executing the tests as indicated by the test flow statements, and binning the IC device as indicated by the results of the tests.

Abstract: The invention is a method for displaying wafer test results from an integrated circuit tester in real time. The method comprising the steps of: (a) receiving wafer dimensions and die dimensions from a wafer handler; (b) creating a template representative of a wafer having cells representative of a die from the wafer dimensions and the die dimensions; (c) displaying the template; (d) invoking a tester to test a selected die of a selected wafer; (e) receiving test results from the tester; (f) displaying the test results on a selected cell which corresponds to the selected die; and (g) repeating steps (d)-(f) as required.