Abstract: A method and apparatus for reducing power in a computer system having a counter and a phase generator. The method consists of receiving an input clock signal which has a plurality of clock cycles and receiving an enable signal. If the enable signal is active, then the counter performs a divide operation. In addition, a block signal is generated when the enable signal is active to hold the output signal in its present state. The block signal is removed if the divide operation is completed or if the enable signal becomes inactive. When the enable signal is not active, then the output signal generated is equal to and in phase with the input clock signal if the enable signal is not active.

Abstract: An apparatus for selecting a clock source in a microprocessor. The apparatus receives a first clock and a second clock. The apparatus has a clock select unit capable of detecting the first clock and selecting between the first clock and the second clock without an external selection signal indicating which clock is to be selected. If the clock selection unit detects the first clock, then the first clock is selected. Otherwise, if the first clock is not detected, then the second clock is selected. The clock selection unit provides an output clock based on the selection.