Patents by Inventor Merii INABA

Merii INABA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10896891
    Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of first pad electrodes provided above the semiconductor substrate; a plurality of first wires electrically connected to the plurality of first pad electrodes respectively; a first electrode commonly connected to the plurality of first wires; a second pad electrode provided above the semiconductor substrate; and a first resistance portion and a first protective element that are connected in series between the first electrode and the second pad electrode.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yu Suzuki, Shoko Kikuchi, Merii Inaba, Jun Murakami, Takashi Shigeoka, Hiroshi Inagaki, Takashi Okuhata
  • Publication number: 20200083192
    Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of first pad electrodes provided above the semiconductor substrate; a plurality of first wires electrically connected to the plurality of first pad electrodes respectively; a first electrode commonly connected to the plurality of first wires; a second pad electrode provided above the semiconductor substrate; and a first resistance portion and a first protective element that are connected in series between the first electrode and the second pad electrode.
    Type: Application
    Filed: March 15, 2019
    Publication date: March 12, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yu Suzuki, Shoko Kikuchi, Merii Inaba, Jun Murakami, Takashi Shigeoka, Hiroshi Inagaki, Takashi Okuhata
  • Patent number: 10050053
    Abstract: According to one embodiment, a semiconductor device includes a substrate and a multilayer body provided on the substrate. The multilayer body has electrode films and insulating films. The electrode films contain silicon, the insulating films contain silicon oxide. Each of the electrode films and each of the insulating films are alternately stacked. A hole is formed in the multilayer body, and the hole vertically extends in the multilayer body. The electrode films include a first electrode film and a second electrode film located below the first electrode film. Carbon concentration of the first electrode film is higher than carbon concentration of the second electrode film.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: August 14, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Merii Inaba
  • Publication number: 20160079256
    Abstract: According to one embodiment, a semiconductor device includes a substrate and a multilayer body provided on the substrate. The multilayer body has electrode films and insulating films. The electrode films contain silicon, the insulating films contain silicon oxide. Each of the electrode films and each of the insulating films are alternately stacked. A hole is formed in the multilayer body, and the hole vertically extends in the multilayer body. The electrode films include a first electrode film and a second electrode film located below the first electrode film. Carbon concentration of the first electrode film is higher than carbon concentration of the second electrode film.
    Type: Application
    Filed: September 2, 2015
    Publication date: March 17, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Merii INABA
  • Publication number: 20160079264
    Abstract: According to one embodiment, a stacked body including electrode layers and first insulating layers; first semiconductor members extending in the stacked body; a second semiconductor member including first portions and a second portion, the second semiconductor member being connected commonly to lower ends of the first semiconductor members; a memory film provided between a first electrode layer of the first electrode layers and one of the first semiconductor members; and an insulating film provided between the second semiconductor member and the stacked body. A second electrode layer of the electrode layers is provided on the second portion of the second semiconductor member via the insulating film. A third electrode layer of the electrode layers is provided under the second portion of the second semiconductor member via the insulating film. One of the first insulating layers is provided between the second electrode layer and the third electrode layer.
    Type: Application
    Filed: March 12, 2015
    Publication date: March 17, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Merii INABA
  • Patent number: 9024443
    Abstract: A semiconductor device according to the present embodiment includes a semiconductor substrate. A lower-layer wiring is provided above a surface of the semiconductor substrate. An interlayer dielectric film is provided on the lower-layer wiring and includes a four-layer stacked structure. A contact plug contains aluminum. The contact plug is filled in a contact hole formed in the interlayer dielectric film in such a manner that the contact plug reaches the lower-layer wiring. Two upper layers and two lower layers in the stacked structure respectively have tapers on an inner surface of the contact hole. The taper of two upper layers and the taper of two lower layers have different angles from each other.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Merii Inaba, Takeshi Hizawa
  • Publication number: 20140061929
    Abstract: A semiconductor device according to the present embodiment includes a semiconductor substrate. A lower-layer wiring is provided above a surface of the semiconductor substrate. An interlayer dielectric film is provided on the lower-layer wiring and includes a four-layer stacked structure. A contact plug contains aluminum. The contact plug is filled in a contact hole formed in the interlayer dielectric film in such a manner that the contact plug reaches the lower-layer wiring. Two upper layers and two lower layers in the stacked structure respectively have tapers on an inner surface of the contact hole. The taper of two upper layers and the taper of two lower layers have different angles from each other.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Merii INABA, Takeshi Hizawa