Abstract: A temperature measurement system is disclosed. In accordance with some embodiments of the present disclosure, a temperature measurement system may comprise a resistor, a thermistor, a resistance-to-current converter configured to generate a current signal based on a resistance, an analog-to-digital converter (ADC) configured to receive a first current signal based on the resistor, convert the first current signal into a first digital signal, receive a second current signal based on the thermistor, and convert the second current signal into a second digital signal, and a calculation stage communicatively coupled to an ADC output and configured to determine a first digital value based on the first digital signal, determine a second digital value based on the second digital signal, calculate a resistance ratio based on the first digital value and the second digital value, and determine a temperature output value based on the resistance ratio.

Abstract: In accordance with some embodiments of the present disclosure, a calibrated temperature measurement system comprises a resistor, a thermistor, a resistance-to-current converter configured to generate a current signal based on a resistance, and an analog-to-digital converter (ADC) configured to receive a first current signal based on the resistor, convert the first current signal into a first digital signal, receive a second current signal based on the thermistor, and convert the second current signal into a second digital signal. A memory may comprise resistor-characterization information. A calculation stage communicatively coupled to an ADC output may be configured to determine a first digital value based on the first digital signal, determine a second digital value based on the second digital signal, calculate a resistance ratio based on the first digital value and the second digital value, and determine a temperature output value based on the resistance ratio and the resistor-characterization information.

Abstract: A temperature-measurement input stage may include a resistor, a thermistor, a first multiplexor, an amplifier, a second multiplexor, and an output stage. The first multiplexor may be configured to couple the resistor to a first amplifier input during a first multiplexor state, and couple the thermistor to the first amplifier input during a second multiplexor state. The amplifier may comprise the first amplifier input, a second amplifier input coupled to a voltage reference, and an amplifier output coupled to a feedback path. The second multiplexor may be configured to route a feedback current to the resistor during the first multiplexor state and route the feedback current to the thermistor during the second multiplexor state. The output stage may be configured to provide an output current based on the feedback current.

Abstract: In accordance with some embodiments of the present disclosure, a calibrated temperature measurement system comprises a resistor, a thermistor, a resistance-to-current converter configured to generate a current signal based on a resistance, and an analog-to-digital converter (ADC) configured to receive a first current signal based on the resistor, convert the first current signal into a first digital signal, receive a second current signal based on the thermistor, and convert the second current signal into a second digital signal. A memory may comprise resistor-characterization information. A calculation stage communicatively coupled to an ADC output may be configured to determine a first digital value based on the first digital signal, determine a second digital value based on the second digital signal, calculate a resistance ratio based on the first digital value and the second digital value, and determine a temperature output value based on the resistance ratio and the resistor-characterization information.

Abstract: A temperature measurement system is disclosed. In accordance with some embodiments of the present disclosure, a temperature measurement system may comprise a resistor, a thermistor, a resistance-to-current converter configured to generate a current signal based on a resistance, an analog-to-digital converter (ADC) configured to receive a first current signal based on the resistor, convert the first current signal into a first digital signal, receive a second current signal based on the thermistor, and convert the second current signal into a second digital signal, and a calculation stage communicatively coupled to an ADC output and configured to determine a first digital value based on the first digital signal, determine a second digital value based on the second digital signal, calculate a resistance ratio based on the first digital value and the second digital value, and determine a temperature output value based on the resistance ratio.

Abstract: A temperature-measurement input stage is disclosed. In accordance with some embodiments of the present disclosure, a temperature-measurement input stage may comprise a resistor, a thermistor, a first multiplexor, an amplifier, a second multiplexor, and an output stage. The first multiplexor may be configured to couple the resistor to a first amplifier input during a first multiplexor state, and couple the thermistor to the first amplifier input during a second multiplexor state. The amplifier may comprise the first amplifier input, a second amplifier input coupled to a voltage reference, and an amplifier output coupled to a feedback path. The second multiplexor may be configured to route a feedback current to the resistor during the first multiplexor state and route the feedback current to the thermistor during the second multiplexor state. The output stage may be configured to provide an output current based on the feedback current.

Abstract: A continuous time delta-sigma modulator is provided that includes an integrator stage including a plurality of integrators; a quantizer to receive an input signal from the integrator stage and output a quantizer signal; a global feedback path providing feedback from the quantizer to the integrator stage; a local feedback path connecting the quantizer and a preceding integrator of the integrator stage configured to compensate for delay attributed to the global feedback path; and a delay compensation circuit. The delay compensation circuit is configured to calculate a delay value based on sources of additional delay within a local feedback loop, and to supply the additional delay value to the quantizer to compensate for delay within the local feedback loop.

Abstract: A differential amplifier circuit with common-mode feedback is disclosed.

Abstract: A differential amplifier circuit with common-mode feedback is disclosed.

Abstract: An integrator circuit (110) is provided including an amplifier element (170) configured to receive an input signal at an input node, amplify the input signal, and provide an amplified input signal at an output node; a feedback capacitor element (175) connected between the output node and the input node; and a current matching circuit (120) connected to the output node, and configured to sense an output voltage of the amplifier element and to provide a supplemental current (IM) to the input node that is less than or equal to a feedback current (IF) charging the feedback capacitor element. This supplemental current is substantially equal and opposite in polarity to a feedback current when the output voltage satisfies a set criterion.

Abstract: An integrator circuit (110) is provided including an amplifier element (170) configured to receive an input signal at an input node, amplify the input signal, and provide an amplified input signal at an output node; a feedback capacitor element (175) connected between the output node and the input node; and a current matching circuit (120) connected to the output node, and configured to sense an output voltage of the amplifier element and to provide a supplemental current (IM) to the input node that is less than or equal to a feedback current (IF) charging the feedback capacitor element. This supplemental current is substantially equal and opposite in polarity to a feedback current when the output voltage satisfies a set criterion.

Abstract: A method and apparatus are provided for operating a feedback network (300, 400). The method and apparatus operate to combine (240) a feedback signal (IF) and an incoming signal (VIN) to generate an adjusted signal (IADJ) at an input node of an amplifier element (110); amplifying the amplifier input signal in the amplifier element to produce an amplifier output signal (VOUT) at an output node of the amplifier element; processing the amplifier output signal according to a feedback operation (230) to generate the feedback signal (IF); and providing an assist current (350, 450, IASSIST) to the output node of the amplifier element, separate from an output current provided by the amplifier element.

Abstract: A double-sampled feedback integrator system includes a sampling module having multiple switched capacitors. The switched capacitors of the integrator system are opened and closed based upon a polarity of the signal input to the double-sampled feedback integrator system. The integrator system can be used in a sigma-delta converter. A sigma-delta converter includes a double-sampled common-mode correction circuit having multiple switched capacitors to provide common-mode rejection to a system.

Abstract: A series capacitive component for use in signal processing applications such as analog-to-digital (A/D) converters, switched capacitor circuits and the like that require matched capacitors is presented. A series capacitive component consists of multiple capacitors connected in series. By utilizing series capacitive components in integrated circuits, significantly lower loads are provided for the same resulting capacitor mismatch range as previous solutions. Additionally, for the same load and noise, using series capacitive components provides a substantially reduced match over previous solutions. Thus a circuit designer has more flexibility when making tradeoffs between circuit area and capacitor mismatch and therefore manufacturing yields.

Abstract: An improved method of filtering that can be used with an analog-to-digital converter (ADC) is disclosed herein. Multiple discrete-time-feedback-modules (114, 116) each with current limiting (202, 204 and 222, 224) are used to sample information which is supplied to an integrator (112) for conversion to digital form. By overlapping the integration of these samples, and by evaluating these integration results multiple times (TP2, TP3, TP4) per sample (TP1), using the methods disclosed herein the advantages of increased accuracy, lower power consumption and reduced cost may be realized.

Abstract: A series capacitive component for use in signal processing applications such as analog-to-digital (A/D) converters, switched capacitor circuits and the like that require matched capacitors is presented. A series capacitive component consists of multiple capacitors connected in series. By utilizing series capacitive components in integrated circuits, significantly lower loads are provided for the same resulting capacitor mismatch range as previous solutions. Additionally, for the same load and noise, using series capacitive components provides a substantially reduced match over previous solutions. Thus a circuit designer has more flexibility when making tradeoffs between circuit area and capacitor mismatch and therefore manufacturing yields.

Abstract: An improved digital-to-analog converter (DAC) is disclosed herein. Multiple switches are used to connect a single current source to one side of a differential output when multiple bits representing the same digital value are received during successive clock cycles. By employing non-overlapping phase clocks, each of the switches can be opened and closed during an appropriate portion of a clock cycle. Using the switch arrangement disclosed herein to connect the current sources to the differential output provides the advantages of increased accuracy, low current draw, and a reduced necessity for current matching multiple current sources.

Abstract: An attribute on a netlist (31) is placed on a layout (33) to allow an automated approach for adding a feature to the layout (33) to be implemented. The netlist (31) or schematic diagram of a circuit is simulated on a Computer Aided Design (CAD) tool to verify circuit functionality. A layout tool (32) generates the layout (33) of the netlist (31). Adding a feature, for example, an extra implant to a source region of a device requires knowledge of device orientation not included in the layout (33). A Layout Versus Schematic (LVS) program (34) is run with the netlist (31) and the layout (33). Connectivity information from the LVS run is retrieved and placed in a connectivity mapping file (35). A mapping program (36) uses the connectivity mapping file (35) and the layout (33) to generate layers indicating and marking device orientation. The layers when added to the layout (33) produce an oriented layout (37).

Abstract: An attribute on a netlist (31) is placed on a layout (33) to allow an automated approach for adding a feature to the layout (33) to be implemented. The netlist (31) or schematic diagram of a circuit is simulated on a Computer Aided Design (CAD) tool to verify circuit functionality. A layout tool (32) generates the layout (33) of the netlist (31). Adding a feature, for example, an extra implant to a source region of a device requires knowledge of device orientation not included in the layout (33). A Layout Versus Schematic (LVS) program (34) is run with the netlist (31) and the layout (33). Connectivity information from the LVS run is retrieved and placed in a connectivity mapping file (35). A mapping program (36) uses the connectivity mapping file (35) and the layout (33) to generate layers indicating and marking device orientation. The layers when added to the layout (33) produce an oriented layout (37).