Abstract: If a predetermined field (FIG. 3/27) within a source instruction indexes and accesses a body of control information from memory (FIG. 2/5), and if control information (FIG. 4) designates the field-to-field (register-to-register) mapping (FIG. 6), then a skeleton target instruction (FIG. 3/29; FIG. 4) can be filled in by either selectively copying the fields of the source instruction or otherwise computing same. If the mapping is executed by an interposed independent processor then overlapping of such conversion enhances throughput, the independent processor converting multifield instructions for a CPU of a first kind to multifield instructions for a CPU of a second kind without disrupting the logical flow or execution of either source or target instruction streams.

Abstract: A microprocessor external instruction feature which provides for a single chip microprocessor with on-chip read only instruction store (ROS) that can also be operated with an off-chip instruction store. To accomplish this, the microprocessor instruction sequencing logic (instruction store, instruction register, instruction counter, and sequencing logic) is duplicated off-chip. An XI MODE input pin signal causes the microprocessor to take its instructions from the external instruction store via 12 XI input pins instead of from the on-chip ROS. A BR DECISION output pin signal from the microprocessor, which indicates that the branch conditions have been met, causes the external instruction counter to be loaded with a branch address from the external instruction register instead of being stepped by external sequencing logic. A WAIT output pin signal causes the external instruction feature logic to suspend operations while the microprocessor is in its wait state.