Abstract: A high frequency signal is converted to a signal characteristic of two simultaneously present, closely spaced high frequency signals. A high frequency signal is passed through a controllable bi-phase modulating switch. The switch is controlled by the resultant output of a multiplier which multiplies the sign of two phase-related pulse trains.

Abstract: A pulsed coherent radar altimeter is described which employs a narrow band receiver and utilizes a novel digital coherent pulse generator. A coherent pulse radar transmits a pulse comprised of the sum of at least two phase related RF signals closely spaced in frequency. The phase shift due to platform motion and return surface irregularity of the return signal is approximately the same for each carrier. The receiver produces a signal representative of the difference of the two carriers which is substantially free of decorrelation effects, and which can be processed in a narrow band receiver to produce range information.

Abstract: Disclosed is a radar apparatus including the circuitry for synchronizing a first and second pulse train, having the same pseudo random coding. The apparatus comprises a programmable delay responsive to a control signal for selectively advancing and retarding a pulse train by monotonic increments. A positive and negative range gate is utilized in passing the video signals in opposite senses in order to generate a command signal for bringing the pulse trains in synchronization.

Abstract: A circuit comprising a signal generating circuit and an interrupt enable circuit. The signal generating circuit has an input connected to receive a trigger signal and an output for generating an output signal which includes a timing cycle of known duration. The signal generating circuit is responsive to the trigger signal for initiating the timing cycle. The interrupt enable circuit is connected to the signal generating circuit for interrupting the timing cycle in timed relation to an interrupt signal and for reinitiating the timing cycle in timed relation to a reset signal, the interrupt enable circuit being connected to receive the interrupt and reset signals. The output signal begins in timed relation to the start pulse and terminates in timed relation to the end of the timing cycle following interruption.

Abstract: Circuitry for generating a virtually jitter free delay relative to a start pulse and for generating such delays over both integer and non-integer multiples of the time interval between timing pulses. The circuitry includes delay circuitry and signal generating circuitry. The delay circuitry is responsive to the start pulse and to the timing pulses for generating first and second signal edges. The second signal edge occurs later in time than the first signal edge, and both signal edges occur following the start pulse and in timed relation to the timing pulses. The signal generating circuitry is connected to the delay circuitry and has an output for generating an output signal which includes a timing cycle of known duration. The signal generating circuitry is responsive to the start pulse for initiating the timing cycle, the first signal edge for interrupting the timing cycle, and the second signal edge for reinitiating the timing cycle.

Abstract: A circuit comprising a signal generating circuit and an interrupt enable circuit. The signal generating circuit has an input connected to receive a trigger signal and an output for generating an output signal which includes a timing cycle of known duration. The signal generating circuit is responsive to the trigger signal for initiating the timing cycle. The interrupt enable circuit is connected to the signal generating circuit for interrupting the timing cycle in timed relation to an interrupt signal and for reinitiating the timing cycle in timed relation to a reset signal, the interrupt enable circuit being connected to receive the interrupt and reset signals. The output signal begins in timed relation to the start pulse and terminates in timed relation to the end of the timing cycle following interruption.

Abstract: Circuitry for generating a virtually jitter free delay relative to a start pulse and for generating such delays over both integer and non-integer multiples of the time interval between timing pulses. The circuitry includes delay circuitry and signal generating circuitry. The delay circuitry is responsive to the start pulse and to the timing pulses for generating first and second signal edges. The second signal edge occurs later in time than the first signal edge, and both signal edges occur following the start pulse and in timed relation to the timing pulses. The signal generating circuitry is connected to the delay circuitry and has an output for generating an output signal which includes a timing cycle of known duration. The signal generating circuitry is responsive to the start pulse for initiating the timing cycle, the first signal edge for interrupting the timing cycle, and the second signal edge for reinitiating the timing cycle.