Patents by Inventor Merrill Albert Hatcher, Jr.

Merrill Albert Hatcher, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955348
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a thermally conductive film, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The thermally conductive film, which has a thermal conductivity greater than 10 W/m·K and an electrical resistivity greater than 1E5 Ohm-cm, resides between the active layer and the first mold compound. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 9, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11869776
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a thermally conductive film, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The thermally conductive film, which has a thermal conductivity greater than 10 W/m·K and an electrical resistivity greater than 1E5 Ohm-cm, resides between the active layer and the first mold compound. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 9, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11664241
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a thermally conductive film, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The thermally conductive film, which has a thermal conductivity greater than 10 W/m·K and an electrical resistivity greater than 1E5 Ohm-cm, resides between the active layer and the first mold compound. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 30, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Publication number: 20230089645
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a thermally conductive film, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The thermally conductive film, which has a thermal conductivity greater than 10 W/m·K and an electrical resistivity greater than 1E5 Ohm-cm, resides between the active layer and the first mold compound. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Application
    Filed: November 29, 2022
    Publication date: March 23, 2023
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11387157
    Abstract: The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: July 12, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11355405
    Abstract: The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: June 7, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11322420
    Abstract: The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 3, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11289392
    Abstract: The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 29, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11257731
    Abstract: The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: February 22, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11063021
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 13, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Patent number: 11011498
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: May 18, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Patent number: 10964672
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 30, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Patent number: 10882740
    Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: January 5, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
  • Patent number: 10804246
    Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 13, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner, Gernot Fattinger, Dirk Robert Walter Leipold, George Maxim, Baker Scott, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Patent number: 10804179
    Abstract: The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: October 13, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Jan Edward Vandemeer, Jonathan Hale Hammond, Merrill Albert Hatcher, Jr., Jon Chadwick
  • Patent number: 10773952
    Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: September 15, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
  • Patent number: 10755992
    Abstract: The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: August 25, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Merrill Albert Hatcher, Jr., Peter V. Wright, Jon Chadwick
  • Publication number: 20200234978
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a thermally conductive film, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The thermally conductive film, which has a thermal conductivity greater than 10 W/m·K and an electrical resistivity greater than 1E5 Ohm-cm, resides between the active layer and the first mold compound. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Application
    Filed: November 8, 2019
    Publication date: July 23, 2020
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, JR.
  • Publication number: 20200235024
    Abstract: The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Application
    Filed: November 8, 2019
    Publication date: July 23, 2020
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, JR.
  • Patent number: 10679918
    Abstract: The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: June 9, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Jan Edward Vandemeer, Jonathan Hale Hammond, Merrill Albert Hatcher, Jr., Jon Chadwick