Abstract: Aspects of the disclosure relate to an apparatus for wireless communication. The apparatus may include a set of power detectors configured to generate a set of analog signals related to a set of output signal power levels of a set of transmit chains of a transmitter, respectively; an analog summer; a set of switching devices configured to send a selected one or more of the set of analog signals to the analog summer, and substantially isolated unselected one or more of the set of power detectors from the analog summer, wherein the analog summer is configured to generate a cumulative analog signal based on a sum of the selected one or more of the set of analog signals; an analog-to-digital converter (ADC) configured to generate a digital signal based on the cumulative analog signal; and a controller configured to control the set of switching devices.

Abstract: Aspects of the disclosure relate to an apparatus for wireless communication. The apparatus may include a set of power detectors configured to generate a set of analog signals related to a set of output signal power levels of a set of transmit chains of a transmitter, respectively; an analog summer; a set of switching devices configured to send a selected one or more of the set of analog signals to the analog summer, and substantially isolated unselected one or more of the set of power detectors from the analog summer, wherein the analog summer is configured to generate a cumulative analog signal based on a sum of the selected one or more of the set of analog signals; an analog-to-digital converter (ADC) configured to generate a digital signal based on the cumulative analog signal; and a controller configured to control the set of switching devices.

Abstract: An example apparatus includes an output jack including a ground pole and a power output pole, a power supply circuit configured to generate a power signal, a coupler circuit operably coupled to the ground pole and the power output pole of the output jack, such that the coupler circuit is configured to couple the power signal with a noise signal on the ground pole to generate a combined output signal on the power output pole.

Abstract: An example apparatus includes an output jack including a ground pole and a power output pole, a power supply circuit configured to generate a power signal, a coupler circuit operably coupled to the ground pole and the power output pole of the output jack, such that the coupler circuit is configured to couple the power signal with a noise signal on the ground pole to generate a combined output signal on the power output pole.

Abstract: An accessory device, configured to be interfaced with a master device, and configured to operate in an analog mode and in a digital mode, the accessory device including: a startup circuit including: a first transistor that interfaces the accessory device to the master device, wherein the first transistor is configured with a first resistive capacitive (RC) circuit to turn on the first transistor according to a time constant of the first RC circuit; a second transistor coupled between ground and the first RC circuit, wherein the second transistor is configured to control a gate of the first transistor in response to a control signal; and a diode having an anode coupled to the first node and a cathode coupled to a body terminal of the first transistor.

Abstract: An interface unit of a mobile device coupled to an auxiliary device, the interface unit including: a first plurality of switches configured for power delivery to the auxiliary device; at least one isolation unit coupled to the first plurality of switches, the at least one isolation unit configured to isolate the multiple signals and to prevent disruption of data communication between the mobile device and the auxiliary device; and a second plurality of switches configured for the data communication between the mobile device and the auxiliary device, the second plurality of switches configured to bypass the at least one isolation unit.

Abstract: A serial data receiver may include an edge detector and a digital integrator. The edge detector may be configured to provide one or more edge detection signals defining an edge detection indication in response to a comparison between two successive samples of a receiver input signal. The edge detection indication may represent a detected negative edge, a detected positive edge, or no detected edge. The digital integrator may be configured to provide a receiver output signal in response to integration of the one or more edge detection signals.

Abstract: A serial data receiver may include an edge detector and a digital integrator. The edge detector may be configured to provide one or more edge detection signals defining an edge detection indication in response to a comparison between two successive samples of a receiver input signal. The edge detection indication may represent a detected negative edge, a detected positive edge, or no detected edge. The digital integrator may be configured to provide a receiver output signal in response to integration of the one or more edge detection signals.

Abstract: An interface unit of a mobile device coupled to an auxiliary device, the interface unit including: a first plurality of switches configured for power delivery to the auxiliary device; at least one isolation unit coupled to the first plurality of switches, the at least one isolation unit configured to isolate the multiple signals and to prevent disruption of data communication between the mobile device and the auxiliary device; and a second plurality of switches configured for the data communication between the mobile device and the auxiliary device, the second plurality of switches configured to bypass the at least one isolation unit.

Abstract: Control circuits for generating output enable signals are disclosed. In one aspect, a control circuit is provided that employs combinatorial logic to generate an output enable signal that meets timing constraints using a standard clock signal, a feedback clock signal based on the standard clock signal, and a single data rate (SDR) data output stream. The control circuit includes a double data rate (DDR) conversion circuit configured to generate a DDR output stream based on a received SDR output stream. The control circuit includes an output enable circuit configured to receive the standard clock signal, feedback clock signal, and DDR output stream, and to generate the output enable signal that is asserted and de-asserted according to the defined timing constraints. The control circuit is configured to generate an accurately timed output enable signal without the need for a fast clock signal in addition to the standard clock signal.

Abstract: Methods for bridging brain sites between which there is substantially no effective communication, and associated neural prosthetic devices, are provided. A neural spike in a first neural site in a subject is detected, and a stimulus to a second neural site in the subject is delivered within a defined period of time after the detection of the neural spike, wherein there is substantially no effective communication between the first and second neural sites. The method forms an artificial bridge between the two neural sites, and establishes lasting communication between the two sites. The present disclosure provides, among other things, a neural prosthetic device comprising an integrated circuit that comprises a recording front-end comprising a plurality of recording channels; a processor unit; and a stimulus delivering back-end comprising a plurality of stimulation channels.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for adjusting a bandwidth of an amplifier (e.g., a programmable gain amplifier (PGA)). In certain aspects, the PGA generally includes at least one amplification stage having an input and an output, a plurality of compensation capacitors, and at least one first switch configured to selectively couple at least one capacitor of the plurality of compensation capacitors between the input and the output of the at least one amplification stage. In certain aspects, the amplifier includes at least one second switch configured to selectively couple the at least one capacitor to a node such that the at least one capacitor is coupled to only one of the output or the node, where a voltage at the node is a differential mode (DM) reference potential for the amplification stage.

Abstract: Methods for bridging brain sites between which there is substantially no effective communication, and associated neural prosthetic devices, are provided. A neural spike in a first neural site in a subject is detected, and a stimulus to a second neural site in the subject is delivered within a defined period of time after the detection of the neural spike, wherein there is substantially no effective communication between the first and second neural sites. The method forms an artificial bridge between the two neural sites, and establishes lasting communication between the two sites. The present disclosure provides, among other things, a neural prosthetic device comprising an integrated circuit that comprises a recording front-end comprising a plurality of recording channels; a processor unit; and a stimulus delivering back-end comprising a plurality of stimulation channels.

Abstract: Control circuits for generating output enable signals are disclosed. In one aspect, a control circuit is provided that employs combinatorial logic to generate an output enable signal that meets timing constraints using a standard clock signal, a feedback clock signal based on the standard clock signal, and a single data rate (SDR) data output stream. The control circuit includes a double data rate (DDR) conversion circuit configured to generate a DDR output stream based on a received SDR output stream. The control circuit includes an output enable circuit configured to receive the standard clock signal, feedback clock signal, and DDR output stream, and to generate the output enable signal that is asserted and de-asserted according to the defined timing constraints. The control circuit is configured to generate an accurately timed output enable signal without the need for a fast clock signal in addition to the standard clock signal.

Abstract: An I/O driver and related method are provided herein. The I/O driver includes circuitry for expediting the configuring of the corresponding output FET to operate in the linear region to reduce delay between the transition of the input signal and the corresponding transition of the output signal. Additionally, the I/O driver includes circuitry for controlling the slew rate at which the output signal transitions from a low logic state to a high logic state, or vice-versa. Further, the I.O driver includes circuitry for turning off the turned-on output FET before turning on the other output FET. This prevents “shoot-thru” current from flowing through the output FETs to reduce power consumption associated with the I/O driver.

Abstract: An apparatus includes an operational amplifier and a plurality of capacitors coupled to an input terminal of the operational amplifier and configured to be selectively coupled to receive one of an input voltage signal and an output voltage signal of the operational amplifier.

Abstract: An integrated DC blocking amplifier circuit, including: an operational amplifier configured in a differential amplifier; and at least first and second two-stage switched-capacitor circuits, each two stage switched-capacitor circuit including a first-stage circuit and a second-stage circuit, wherein the first two-stage switched capacitor circuit is connected to a positive side feedback path of the operational amplifier and the second two-stage switched capacitor circuit is connected to a negative side feedback path of the operational amplifier, wherein the first-stage circuit is switched at a relatively low switching frequency, while the second-stage circuit is switched at a relatively high switching frequency.

Abstract: An apparatus includes a transmission gate configured to generate a signal based on a first differential input signal and a second differential input signal. The apparatus further includes biasing circuitry responsive to the transmission gate and configured to output a bias voltage based on the signal.

Abstract: An apparatus includes an operational amplifier and a plurality of capacitors coupled to an input terminal of the operational amplifier and configured to be selectively coupled to receive one of an input voltage signal and an output voltage signal of the operational amplifier.

Abstract: An integrated DC blocking amplifier circuit, including: an operational amplifier configured in a differential amplifier; and at least first and second two-stage switched-capacitor circuits, each two stage switched-capacitor circuit including a first-stage circuit and a second-stage circuit, wherein the first two-stage switched capacitor circuit is connected to a positive feedback path of the operational amplifier and the second two-stage switched capacitor circuit is connected to a negative feedback path of the operational amplifier, wherein the first-stage circuit is switched at a relatively low switching frequency, while the second-stage circuit is switched at a relatively high switching frequency.