Abstract: A liquid crystal display includes a first display substrate, a second display substrate facing the first display substrate, and a liquid crystal layer interposed between the first and second display substrates, where the first display substrate includes a lower substrate, a pixel electrode, which is disposed on the lower substrate, and a protrusion pattern, which is disposed on the pixel electrode along an outer edge of the pixel electrode, the second display substrate includes an upper substrate and a light-shielding member, which is disposed on a surface of the upper substrate facing the first display substrate and in which indentation pattern parts are inwardly indented in a plan view, the light-shielding member includes light-shielding parts that are an entirety of the light-shielding member except for the indentation pattern parts, and the indentation pattern parts overlap parts of the pixel electrode.

Abstract: A semiconductor memory device may include a sense amplifier for sensing and amplifying data of a bit line pair with pull-up and pull-down driving voltages; a voltage supplier for supplying a power supply voltage or an internal voltage lower than the power supply voltage as the pull-up driving voltage through a pull-up power supply line in response to a first or second pull-up control signal, and supplying a ground voltage as the pull-down driving voltage through a pull-down power supply line in response to a pull-down control signal; a voltage detector for detecting a voltage level of the power supply voltage and outputting a detection signal; and a control signal generator for generating the first and second pull-up control signals, and the pull-down control signal and delaying an enabling timing of one of the first pull-up and pull-down control signals in response to the detection signal.

Abstract: A semiconductor memory device may include a sense amplifier for sensing and amplifying data of a bit line pair with pull-up and pull-down driving voltages; a voltage supplier for supplying a power supply voltage or an internal voltage lower than the power supply voltage as the pull-up driving voltage through a pull-up power supply line in response to a first or second pull-up control signal, and supplying a ground voltage as the pull-down driving voltage through a pull-down power supply line in response to a pull-down control signal; a voltage detector for detecting a voltage level of the power supply voltage and outputting a detection signal; and a control signal generator for generating the first and second pull-up control signals, and the pull-down control signal and delaying an enabling timing of one of the first pull-up and pull-down control signals in response to the detection signal.

Abstract: A semiconductor memory device may include a sense amplifier for sensing and amplifying data of a bit line pair with pull-up and pull-down driving voltages; a voltage supplier for supplying a power supply voltage or an internal voltage lower than the power supply voltage as the pull-up driving voltage through a pull-up power supply line in response to a first or second pull-up control signal, and supplying a ground voltage as the pull-down driving voltage through a pull-down power supply line in response to a pull-down control signal; a voltage detector for detecting a voltage level of the power supply voltage and outputting a detection signal; and a control signal generator for generating the first and second pull-up control signals, and the pull-down control signal and delaying an enabling timing of one of the first pull-up and pull-down control signals in response to the detection signal.

Abstract: A liquid crystal display includes a pixel electrode which includes a first subpixel electrode and a second subpixel electrode, a first insulating substrate and a second insulating substrate which faces the first insulating substrate, a common electrode which overlaps the pixel region, where the first subpixel electrode includes a first main unit electrode and a first sub unit electrode which is electrically connected to the first main unit electrode and smaller in area than the first main unit electrode, the second subpixel electrode includes a second main unit electrode, and a first opening part which overlaps the first main unit electrode, a second opening part which overlaps the second main unit electrode, and a third opening part which overlaps the first sub unit electrode and has a different shape from those of the first opening part and the second opening part are defined in the common electrode.

Abstract: An operating method of a memory device including a plurality of memory cells may include: measuring data retention times of at least a portion of the plurality of memory cells; and optimizing a refresh operation on the plurality of memory cells using the measurement result.

Abstract: A liquid crystal display includes a first display substrate, a second display substrate facing the first display substrate, and a liquid crystal layer interposed between the first and second display substrates, where the first display substrate includes a lower substrate, a pixel electrode, which is disposed on the lower substrate, and a protrusion pattern, which is disposed on the pixel electrode along an outer edge of the pixel electrode, the second display substrate includes an upper substrate and a light-shielding member, which is disposed on a surface of the upper substrate facing the first display substrate and in which indentation pattern parts are inwardly indented in a plan view, the light-shielding member includes light-shielding parts that are an entirety of the light-shielding member except for the indentation pattern parts, and the indentation pattern parts overlap parts of the pixel electrode.

Abstract: A semiconductor memory device may include a sense amplifier for sensing and amplifying data of a bit line pair with pull-up and pull-down driving voltages; a voltage supplier for supplying a power supply voltage or an internal voltage lower than the power supply voltage as the pull-up driving voltage through a pull-up power supply line in response to a first or second pull-up control signal, and supplying a ground voltage as the pull-down driving voltage through a pull-down power supply line in response to a pull-down control signal; a voltage detector for detecting a voltage level of the power supply voltage and outputting a detection signal; and a control signal generator for generating the first and second pull-up control signals, and the pull-down control signal and delaying an enabling timing of one of the first pull-up and pull-down control signals in response to the detection signal.

Abstract: A liquid crystal display includes a pixel electrode which includes a first subpixel electrode and a second subpixel electrode, a first insulating substrate and a second insulating substrate which faces the first insulating substrate, a common electrode which overlaps the pixel region, where the first subpixel electrode includes a first main unit electrode and a first sub unit electrode which is electrically connected to the first main unit electrode and smaller in area than the first main unit electrode, the second subpixel electrode includes a second main unit electrode, and a first opening part which overlaps the first main unit electrode, a second opening part which overlaps the second main unit electrode, and a third opening part which overlaps the first sub unit electrode and has a different shape from those of the first opening part and the second opening part are defined in the common electrode.

Abstract: A semiconductor memory apparatus comprises bit line sense amplifier unit, and a pair of precharge elements coupled in series between a first bit line and a second bit line and having an asymmetrical contact resistance ratio.

Abstract: A data transmission circuit includes a read data transmission unit configured to, when a read signal is asserted, detect and amplify a voltage level of a first data line, transmit an amplified voltage level to a second data line, and substantially prevent a voltage level of the second data line from being amplified to be substantially equal to or more than a preset voltage level, and a write data transmission unit configured to transmit the voltage level of the second data line to the first data line when a write signal is asserted.

Abstract: A data transmission circuit includes a read data transmission unit configured to, when a read signal is asserted, detect and amplify a voltage level of a first data line, transmit an amplified voltage level to a second data line, and substantially prevent a voltage level of the second data line from being amplified to be substantially equal to or more than a preset voltage level, and a write data transmission unit configured to transmit the voltage level of the second data line to the first data line when a write signal is asserted.

Abstract: A semiconductor memory apparatus comprise s bit line sense amplifier unit, and a pair of precharge elements coupled in series between a first bit line and a second bit line and having an asymmetrical contact resistance ratio.

Abstract: A semiconductor apparatus includes a first capacitor formed in a normal cell area and including a lower electrode coupled to one end of a cell transistor, and a second capacitor formed in a dummy cell area and including a lower electrode coupled to a power terminal.

Abstract: A semiconductor device includes a fuse box including a plurality of fuses and a plurality of common nodes, wherein paired fuses among the plurality of fuses are aligned in a first direction and the plurality of common nodes between fuses of each of the pairs at a different height is aligned in a second direction perpendicular to the first direction.

Abstract: A method for forming a fuse in a semiconductor device is disclosed. The method for forming the fuse in the semiconductor device forms an interlayer insulating layer when forming a fuse, and forms neighboring metal lines having different thicknesses using a zigzag-opened mask, thus preventing a neighboring fuse of a fuse to be blown from being damaged. A method for manufacturing the semiconductor device deposits a first interlayer insulating layer on a semiconductor substrate, patterns the first interlayer insulating layer using a zigzag-opened pad type mask such that the first interlayer insulating layer has different step heights where the same step height is arranged at every second step height location, deposits a second interlayer insulating layer, patterns the second interlayer insulating layer, and buries a metal on an entire surface, and planarizes the metal until the second interlayer insulating layer is exposed, thus forming a metal pattern.