Abstract: The present invention relates to a device capable of wrapping the outer wall of a blood vessel, and a method for manufacturing the device. If the device for wrapping the outer wall of a blood vessel of the present invention is used, the outer wall of a blood vessel is wrapped, and, thereby, vortex generation can be significantly decreased by controlling abnormal expansion of the blood vessel which can occur due to the difference in the characteristics of blood vessels in a vein-artery graft model. The present invention saves a blood vessel from a low-oxygen state by promoting generation of new blood vessels on the outer wall of the blood vessel via a regenerative inflammatory response caused by the material of the device, and provides synergy effects such as prevention of vascular stenosis and reinforcement of an outer muscular layer by guiding venous muscular cells to the outside.

Abstract: The present disclosure relates to an organic electroluminescent compound and an organic electroluminescent device comprising the same. By comprising the compound according to the present disclosure, it is possible to produce an organic electroluminescent device having improved driving voltage, power efficiency, and/or lifetime properties compared to the conventional organic electroluminescent devices.

Abstract: The present disclosure relates to an organic electroluminescent compound, a plurality of host materials, and an organic electroluminescent device comprising the same. By comprising the compound according to the present disclosure or by comprising a specific combination of compounds according to the present disclosure as a plurality of host materials, it is possible to produce an organic electroluminescent device having improved driving voltage, luminous efficiency, and/or lifetime properties compared to the conventional organic electroluminescent devices.

Abstract: The present invention provides a pharmaceutical composition and a treatment method to be combined with radiotherapy, for treatment of triple negative breast cancer. More specifically, the pharmaceutical composition comprises a PD-1 blockade and a PI3K? ? inhibitor, and it has excellent effects of inhibiting tumor and enhancing immunity by combining the PD-1 blockade and PI3K? ? inhibitor with radiotherapy, compared to single therapy of each therapeutic agent.

Abstract: The present invention provides a pharmaceutical composition and a treatment method to be combined with radiotherapy, for treatment of triple negative breast cancer. More specifically, the pharmaceutical composition comprises a PD-1 blockade and a PI3K ? ? inhibitor, and it has excellent effects of inhibiting tumor and enhancing immunity by combining the PD-1 blockade and PI3K ? ? inhibitor with radiotherapy, compared to single therapy of each therapeutic agent.

Abstract: Provided are an apparatus and a method for simulating a semiconductor device. The method includes: modeling, through an input interface of a simulation device, a flat transistor as a first transistor; modeling, through the input interface, a first corner transistor as a second transistor; and calculating, by a processor of the simulation device, an output electrical signal in response to an input electrical signal applied to the first transistor and the second transistor to simulate at least one electrical characteristic of the semiconductor device. The flat transistor is formed by an active region defined by an isolation region on a semiconductor substrate, a gate electrode extending from the isolation region across the active region, and an impurity region in a portion of the active region. The first corner transistor is formed by an overlapping of the gate electrode and a first edge portion of the active region.

Abstract: Provided are an apparatus and a method for simulating a semiconductor device. The method includes: modeling, through an input interface of a simulation device, a flat transistor as a first transistor; modeling, through the input interface, a first corner transistor as a second transistor; and calculating, by a processor of the simulation device, an output electrical signal in response to an input electrical signal applied to the first transistor and the second transistor to simulate at least one electrical characteristic of the semiconductor device. The flat transistor is formed by an active region defined by an isolation region on a semiconductor substrate, a gate electrode extending from the isolation region across the active region, and an impurity region in a portion of the active region. The first corner transistor is formed by an overlapping of the gate electrode and a first edge portion of the active region.

Abstract: A semiconductor integrated circuit device includes a first dopant region in a semiconductor substrate, an isolation region on the semiconductor substrate, the isolation region surrounding the first dopant region, a gate wire surrounding at least a portion of the isolation region, and a plurality of second dopant regions arranged along at least a portion of the gate wire, the plurality of second dopant regions being spaced apart from each other, and the portion of the gate wire being between the first dopant region and a respective second dopant region.

Abstract: A semiconductor integrated circuit device includes a first dopant region in a semiconductor substrate, an isolation region on the semiconductor substrate, the isolation region surrounding the first dopant region, a gate wire surrounding at least a portion of the isolation region, and a plurality of second dopant regions arranged along at least a portion of the gate wire, the plurality of second dopant regions being spaced apart from each other, and the portion of the gate wire being between the first dopant region and a respective second dopant region.

Abstract: In a HV transistor having a high breakdown voltage and a method of manufacturing the same, a first insulation pattern is formed on a semiconductor substrate by oxidizing a portion of the substrate, and a second insulation pattern is formed such that at least a portion of the first insulation pattern is covered with the second insulation pattern. A gate electrode including a first end portion and a second end portion opposite to the first end portion is formed on the substrate by depositing conductive materials onto the substrate. The first end portion is formed on the first insulation pattern and the second end portion is formed on the second insulation pattern. Source/drain regions are formed at surface portions of the substrate by implanting impurities onto the substrate. Electric field intensity at an edge portion of the gate electrode is reduced, and the HV transistor has a high breakdown voltage.

Abstract: A method of forming a high voltage semiconductor device includes forming a thermal oxide layer on a semiconductor substrate where a trench is formed, forming a chemical vapor deposition (CVD) oxide layer on the thermal oxide layer, and etching the CVD oxide layer and the thermal oxide layer at different etching selectivities to form a gate insulating layer having an inclined sidewall and a device isolation pattern. Thus, a gate insulating layer having a sufficiently large thickness and a device isolation pattern can be formed simultaneously by means of simple process steps and degradation of the device can be suppressed even when a high voltage is applied.

Abstract: In a HV transistor having a high breakdown voltage and a method of manufacturing the same, a first insulation pattern is formed on a semiconductor substrate by oxidizing a portion of the substrate, and a second insulation pattern is formed such that at least a portion of the first insulation pattern is covered with the second insulation pattern. A gate electrode including a first end portion and a second end portion opposite to the first end portion is formed on the substrate by depositing conductive materials onto the substrate. The first end portion is formed on the first insulation pattern and the second end portion is formed on the second insulation pattern. Source/drain regions are formed at surface portions of the substrate by implanting impurities onto the substrate. Electric field intensity at an edge portion of the gate electrode is reduced, and the HV transistor has a high breakdown voltage.