Abstract: A memory device including a memory cell array which includes a plurality of memory cells connected to each of a plurality of bit lines and word lines, a first bit line sense amplifier electrically connected to a first bit line through a first memory cell and a first connecting wiring and a second bit line sense amplifier electrically connected to a second bit line through a second connecting wiring having a length different from that of the first connecting wiring. A first compensation load of the first bit line and a second compensation load of the second bit line are adjusted to equalize RC loads of the first bit line and the second bit line.

Abstract: A pixel includes first, second, and third sub-pixels each including an emission area and a non-emission area. Each of the first, second, and third sub-includes a pixel circuit layer; a first electrode on the pixel circuit layer; a pixel defining layer on the first electrode and including an opening to expose an area of the first electrode; an emission layer on the pixel defining layer; a second electrode on the emission layer; a thin film encapsulation layer over the second electrode; a color filter on the thin film encapsulation layer; and an overcoat layer over the color filter. The overcoat layer has a refractive index greater than a refractive index of the color filter. A color filter of the second sub-pixel overlaps a color filter of each of the first and third sub-pixels in the non-emission area.

Abstract: A memory device is provided. The memory device comprises a memory cell array connected to a first bit line and a complementary bit line, a first bit line sense amplifier configured to sense, amplify and the first bit line signal output a first bit line signal and the complimentary bit signal output on a complementary bit line signal output on the first bit line and the complementary bit line, a charge transfer transistor connected to the first bit line sense amplifier and configured to be gated by a charge transfer signal of a first node, an offset transistor configured to connect the first node and a second node based on an offset removal signal and a pre-charging transistor connected between the second node and a pre-charging voltage line and the pre-charging transistor being configured to pre-charge the first bit line or the complementary bit line based on an equalizing signal.