Patents by Inventor Mir IM

Mir IM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978626
    Abstract: In a method of treating a target film, a plurality of pattern structures with sidewall surfaces facing each other are provided. A target film is formed on the sidewalls of the plurality of pattern structures. A plurality of nanoparticles are distributed on the target thin film. The target thin film is thermally treated by irradiating laser light from upper sides of the plurality of pattern structures to the target thin film. The irradiated laser light is scattered from the plurality of nanoparticles.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: May 7, 2024
    Assignee: SK hynix Inc.
    Inventors: Won Tae Koo, Mir Im
  • Publication number: 20240105602
    Abstract: A semiconductor device according to an embodiment includes a first stacked structure including a first base body, a first connection pad disposed over a surface of the first base body, and a first pad buffer layer disposed adjacent to the first connection pad and the first pad buffer layer including an insulating material having a porous structure. In addition, the semiconductor device includes a second stacked structure including a second base body, a second connection pad disposed over a surface of the second base body, and a second pad buffer layer disposed adjacent to the second connection pad and the second pad buffer layer including an insulating material having a porous structure. The semiconductor device includes a connection portion of the first and second stacked structures that connects the first and second connection pads.
    Type: Application
    Filed: March 30, 2023
    Publication date: March 28, 2024
    Inventors: Mir IM, Won Tae KOO
  • Publication number: 20240008282
    Abstract: A semiconductor device according to an embodiment includes a substrate, a source electrode layer and a drain electrode layer that are disposed over the substrate to be spaced apart from each other in a direction substantially perpendicular to a surface of the substrate, first and second oxide channel layers the extend in the direction substantially perpendicular to the surface of the substrate between the source electrode layer and the drain electrode layer, a ferroelectric layer disposed adjacent to the first and second oxide channel layers, and a gate electrode layer disposed on the ferroelectric layer. The first and second oxide channel layers have different band gap energies from each other.
    Type: Application
    Filed: November 29, 2022
    Publication date: January 4, 2024
    Inventor: Mir IM
  • Publication number: 20230413573
    Abstract: A semiconductor device includes: a first memory including first capacitors that are vertically stacked in a first direction; and a second memory that is laterally spaced apart from the first memory in a second direction and that includes second capacitors that are vertically stacked in the first direction. The first capacitors may include ferroelectric capacitors, and the second capacitors may include paraelectric capacitors.
    Type: Application
    Filed: November 30, 2022
    Publication date: December 21, 2023
    Inventor: Mir IM
  • Publication number: 20230292484
    Abstract: A semiconductor device according to an embodiment of the present disclosure includes a read transistor and a write transistor that are electrically connected to each other over a substrate. The read transistor includes a read channel layer disposed on a plane over the substrate, a read gate dielectric layer disposed over the read channel layer, and a read gate electrode layer disposed over the read gate dielectric layer. The write transistor includes a write channel layer disposed over a portion of the read gate electrode layer, a write bit line disposed on an upper surface of the write channel layer, a write gate dielectric layer on a side surface of the write channel layer, and a write word line disposed to be adjacent to the write gate dielectric layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: September 14, 2023
    Inventor: Mir IM
  • Publication number: 20230260956
    Abstract: In an embodiment, a method of fabricating a semiconductor device includes providing a first substrate structure, the first substrate structure including a first substrate body, a first conductive connection structure and a first two-dimensional inorganic layer having negative charges disposed adjacent to each other over the first substrate body, providing a second substrate structure, the second substrate structure including a second substrate body, a second conductive connection structure and a second two-dimensional inorganic layer having negative charges disposed adjacent to each other over the second substrate body, and joining the first and second substrate structure to each other such that the first conductive connection structure and the second conductive connection structure are connected to each other, and the first two-dimensional inorganic layer and the second two-dimensional inorganic layer are joined to each other.
    Type: Application
    Filed: July 13, 2022
    Publication date: August 17, 2023
    Inventor: Mir IM
  • Publication number: 20230247840
    Abstract: A semiconductor device according to an embodiment includes a substrate, a bit line structure and a source line structure each extending in a direction perpendicular to a surface of the substrate, a semiconductor layer disposed between the bit line structure and the source line structure on a plane parallel to the surface of the substrate, a ferroelectric layer disposed on the semiconductor layer and including a ferroelectric superlattice structure, and a gate electrode layer disposed on the ferroelectric layer.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 3, 2023
    Inventors: Mir IM, Jae Gil LEE
  • Publication number: 20230197142
    Abstract: A semiconductor device according to an embodiment of the present disclosure includes a write transistor and a read transistor disposed over a substrate. The write transistor includes a write word line disposed on a plane that is substantially parallel to a surface of the substrate over the substrate, a write gate dielectric layer disposed over the write word line, a write channel layer disposed over the write gate dielectric layer, and a write bit line disposed over the substrate and extending in a direction substantially perpendicular to a surface of the substrate, and electrically connected to one end of the write channel layer. The read transistor includes a read channel layer disposed on the plane over the substrate, a read gate dielectric layer disposed over the read channel layer, and a read gate electrode layer disposed over the read gate dielectric layer and electrically connected to the other end of the write channel layer.
    Type: Application
    Filed: May 19, 2022
    Publication date: June 22, 2023
    Inventor: Mir IM
  • Publication number: 20230171946
    Abstract: A semiconductor device includes: a substrate; a seed layer over the substrate; a perovskite-based channel layer over the seed layer; a bit line coupled to one side of the perovskite-based channel layer and extending in a direction perpendicular to the substrate; a capacitor coupled to another side of the perovskite-based channel layer; a word line crossing an upper surface of the perovskite-based channel layer; and a gate dielectric layer disposed between the word line and the perovskite-based channel layer.
    Type: Application
    Filed: June 23, 2022
    Publication date: June 1, 2023
    Inventor: Mir IM
  • Publication number: 20230122541
    Abstract: A semiconductor device includes a memory cell including a write transistor and a read transistor that are electrically connected to each other. The write transistor includes a write bit line disposed over a substrate, a write channel structure disposed on the write bit line and extending in a direction perpendicular to a surface of the substrate on the write bit line, a write gate dielectric layer disposed on a side surface of the write channel structure, and a write word line disposed on the write gate dielectric layer. The read transistor includes a read gate electrode layer disposed on the write channel structure, a read gate dielectric layer disposed on the read gate electrode layer, a read channel layer disposed on the read gate dielectric layer, and a read word line and a read bit line that are disposed at opposite ends of the read channel layer.
    Type: Application
    Filed: May 26, 2022
    Publication date: April 20, 2023
    Inventor: Mir IM
  • Publication number: 20230096911
    Abstract: A capacitor includes: a bottom electrode; a top electrode; and a hybrid dielectric layer including at least one nanosheet material disposed between the bottom electrode and the top electrode.
    Type: Application
    Filed: March 16, 2022
    Publication date: March 30, 2023
    Inventor: Mir IM
  • Publication number: 20230035006
    Abstract: A semiconductor memory device comprises: a laterally oriented hybrid channel including outer channel materials and an inner channel material interposed between the outer channel materials; a laterally oriented double word line with the hybrid channel interposed therebetween; a vertically oriented bit line connected to a first end of the hybrid channel; and a capacitor connected to a second end of the hybrid channel.
    Type: Application
    Filed: February 22, 2022
    Publication date: February 2, 2023
    Inventor: Mir IM
  • Publication number: 20230005742
    Abstract: In a method of treating a target film, a plurality of pattern structures with sidewall surfaces facing each other are provided. A target film is formed on the sidewalls of the plurality of pattern structures. A plurality of nanoparticles are distributed on the target thin film. The target thin film is thermally treated by irradiating laser light from upper sides of the plurality of pattern structures to the target thin film. The irradiated laser light is scattered from the plurality of nanoparticles.
    Type: Application
    Filed: December 9, 2021
    Publication date: January 5, 2023
    Inventors: Won Tae KOO, Mir IM