Abstract: One aspect of the present disclosure is a pharmaceutical composition which includes (R)—N-[1-(3,5-difluoro-4-methansulfonylamino-phenyl)-ethyl]-3-(2-propyl-6-trifluoromethyl-pyridin-3-yl)-acrylamide as a first component and a cellulosic polymer as a second component, wherein the composition of one aspect of the present disclosure has a formulation characteristic in which crystal formation is delayed for a long time.

Abstract: A semiconductor device may include a first terminal electrically connected to a first semiconductor chip, a second terminal electrically connected to a second semiconductor chip, which is different from the first semiconductor chip, a first signal line electrically connecting the first terminal and the second terminal and including a first node, a third terminal connected to a tester monitoring a signal transmitted between the first semiconductor chip and the second semiconductor chip, a fourth terminal applied a reference voltage, a second signal line electrically connecting the third terminal and the fourth terminal and including a second node, a first resistor connected between the first node and the second node and a second resistor directly connected to the second node different from the first resistor.

Abstract: A data processing system includes a first memory, a second memory, a temperature sensor, and a controller. The temperature sensor is configured to sense a temperature at the data processing system and generate a temperature signal. The controller is configured to control whether the first memory is enabled or disabled and whether the second memory is enabled or disabled based on the temperature signal and based on a first temperature threshold associated with the first memory and a second temperature threshold associated with the second memory.

Abstract: A semiconductor device may include a first terminal electrically connected to a first semiconductor chip, a second terminal electrically connected to a second semiconductor chip, which is different from the first semiconductor chip, a first signal line electrically connecting the first terminal and the second terminal and including a first node, a third terminal connected to a tester monitoring a signal transmitted between the first semiconductor chip and the second semiconductor chip, a fourth terminal applied a reference voltage, a second signal line electrically connecting the third terminal and the fourth terminal and including a second node, a first resistor connected between the first node and the second node and a second resistor directly connected to the second node different from the first resistor.

Abstract: A method is provided for operating a volatile memory device. The method includes performing a first initialization operation for the volatile memory device based on a boot code received from an external memory controller, storing the boot code in an internal register, reading the boot code stored in the internal register based on a first signal received from the external memory controller when the first initialization operation is not normally performed, and performing a second initialization operation for the volatile memory device based on the boot code read from the internal register.

Abstract: A data processing system includes a first memory, a second memory, a temperature sensor, and a controller. The temperature sensor is configured to sense a temperature at the data processing system and generate a temperature signal. The controller is configured to control whether the first memory is enabled or disabled and whether the second memory is enabled or disabled based on the temperature signal and based on a first temperature threshold associated with the first memory and a second temperature threshold associated with the second memory.

Abstract: Provides is a multi-chip package including a plurality of semiconductor memory devices. Each of semiconductor memory devices includes a register and a control circuit. The register is configured to store start sequence information representing start of execution of a refresh operation in the multi-chip package. The control circuit is configured to control start of the execution of the refresh operation in response to the start sequence information stored in the register. Since the start of the execution of the refresh operation is performed in sequence of respective semiconductor memory devices according to the start sequence information stored in the register, consumption of peak current may be reduced in a power saving mode.

Abstract: Provides is a multi-chip package including a plurality of semiconductor memory devices. Each of semiconductor memory devices includes a register and a control circuit. The register is configured to store start sequence information representing start of execution of a refresh operation in the multi-chip package. The control circuit is configured to control start of the execution of the refresh operation in response to the start sequence information stored in the register. Since the start of the execution of the refresh operation is performed in sequence of respective semiconductor memory devices according to the start sequence information stored in the register, consumption of peak current may be reduced in a power saving mode.

Abstract: A method is provided for operating a volatile memory device. The method includes performing a first initialization operation for the volatile memory device based on a boot code received from an external memory controller, storing the boot code in an internal register, reading the boot code stored in the internal register based on a first signal received from the external memory controller when the first initialization operation is not normally performed, and performing a second initialization operation for the volatile memory device based on the boot code read from the internal register.

Abstract: An ODT circuit performs termination control on at least one pair of differential mode signals within a memory chip. The ODT circuit may include a switching unit. The switching unit may include a plurality of switching blocks. The switching blocks may include termination resistance devices connected in parallel between first and second differential signal lines, and connect the termination resistance devices with the differential signal lines during operation in response to an applied switching control signal.

Abstract: A memory system capable of reducing electromagnetic interference in data lines includes a memory controller and a synchronous semiconductor memory device. The memory controller controls the phases of write data strobe signals, which fetch write data transmitted through respective data lines. The synchronous semiconductor memory device receives the write data and controls the phases of read data strobe signals to be different from each other.