Patents by Inventor Miaki Nakashio

Miaki Nakashio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4876703
    Abstract: In an apparatus having a CCD for compressing and/or expanding the time base of an input signal; a first two-phase transfer clock pulse signal made up of first and second pulse train signals having a first period and arranged to be 180.degree. out of phase with each other is used for driving the CCD while writing the input signal into the CCD, a second two-phase transfer clock pulse signal made up of third and fourth pulse train signals having a second period and arranged to be 180.degree. out of phase with each other is used for driving the CCD while reading from the CCD a signal which is produced from the input signal with its time base compressed or expanded, and the pulse width of the first pulse train signal is made virtually equal to the pulse width of the third pulse train signal and such pulse width is selected to be smaller than one-half of the smaller of the first and second periods.
    Type: Grant
    Filed: February 24, 1988
    Date of Patent: October 24, 1989
    Assignee: Sony Corp.
    Inventors: Kaoru Urata, Miaki Nakashio, Koichi Ono, Hitoshi Hirai, Masayuki Iwamoto
  • Patent number: 4621369
    Abstract: An input circuit for a charge transfer device in which within a region of the input gate of its charge transfer element the potential barrier same as that in the transfer section thereof is provided and the same digital input signal is supplied to a pair of input gates.
    Type: Grant
    Filed: October 20, 1983
    Date of Patent: November 4, 1986
    Assignee: Sony Corporation
    Inventors: Tadakuni Narabu, Takeo Hashimoto, Hideo Kanbe, Maki Sato, Miaki Nakashio
  • Patent number: 4558341
    Abstract: A charge transfer device having a plurality of first storage regions separated from one other by a first channel stopper region and arranged along one direction, a plurality of second storage regions opposed to the first storage regions and separated from one other by a second channel stopper region and arranged along the one direction, and first and second transfer regions placed between the first and second storage regions and arranged alternately along the one direction is disclosed, in which the first and second storage regions are displaced from one other with respect to the one direction, the adjoining first and second transfer regions along the one direction are paired, each of the pairs is in common contact with the first storage regions and is in respective contact with the separated and adjoining second storage regions, and the first and second storage regions are partially protruded to the first and second transfer regions to form protrusive portions.
    Type: Grant
    Filed: April 19, 1983
    Date of Patent: December 10, 1985
    Assignee: Sony Corporation
    Inventors: Tadakuni Narabu, Miaki Nakashio