Abstract: Systems and methods for performing pin-pull testing of a printed circuit board (PCB) are presented. The pin-pull testing generally involves the use of a standard tensile tester that is useful for performing other tests aside from pin-pull testing. In this regard, a non-specific pin may be used in conjunction with the tensile tester without the need to purchase or manufacture pins specially adapted for use with a specially designed tensile tester. Additionally, the pin-pull testing may include application of heat to the pin by way of an external heat supply such that the need of a heater integrated into the testing device to heat a pin during the testing may be eliminated. As such, a common heating element (e.g., a standard soldering iron) may be employed by applying heat to a pin directly with the external heat supply.

Abstract: A stacked inductor with different metal thickness and metal width. The stacked inductor comprises top and bottom metal traces which are aligned with each other. The thickness and width of the top and bottom metal traces are different. The top and bottom metal traces are connected at the end of metal trace with via holes. The inductance is increased with the use of the mutual inductance between top and bottom metal layers The parasitic resistor is reduced due to the difference of the top and bottom metal widths.

Abstract: A stacked inductor with combined metal layers is represented in this invention. The stacked inductor includes: a top layer metal coil, and at least two lower layer metal coils, the metal coils being aligned with each other; adjacent metal coils being connected at the corresponding ends through a via; wherein, each of the lower layer metal coils is consisted of plural layers of metal lines which are interconnected. With the same chip area, the stacked inductor of the present invention can achieve higher inductance and Q factor because of the mutual inductance generated from the plural layers of metal lines and the reduced parasitic resistance.

Abstract: Systems and methods for performing pin-pull testing of a printed circuit board (PCB) are presented. The pin-pull testing generally involves the use of a standard tensile tester that is useful for performing other tests aside from pin-pull testing. In this regard, a non-specific pin may be used in conjunction with the tensile tester without the need to purchase or manufacture pins specially adapted for use with a specially designed tensile tester. Additionally, the pin-pull testing may include application of heat to the pin by way of an external heat supply such that the need of a heater integrated into the testing device to heat a pin during the testing may be eliminated. As such, a common heating element (e.g., a standard soldering iron) may be employed by applying heat to a pin directly with the external heat supply.

Abstract: A stacked inductor with different metal thickness and metal width is represented in this invention, this structure comprise: top and bottom metal trace, which is aligned with each other. The thickness and width of top and bottom metal trace are different. The top and bottom metal trace are connected at the end of metal trace with via holes. The inductance is increased with the use of the mutual inductance between top and bottom metal layers, and the parasitic resistor is reduced by means of different top and bottom metal width. This stacked inductor possesses larger inductance than single layer spiral inductor with relatively higher Q factor.

Abstract: A manufacture method for IC process with top and top-1 metal layers thickened and stacked inductor manufactured by this method is represented in this invention. This method includes: with multi metal layers, and the thickness of top and top-1 metal layers are more than 2.8 um. Thickened top and top-1 metal layers can reduce the resistance of top and top-1 metal layers, so can increase the Q factor of inductor.

Abstract: A stacked inductor with combined metal layers is represented in this invention. The stacked inductor includes: a top layer metal coil, and at least two lower layer metal coils, the metal coils being aligned with each other; adjacent metal coils being connected at the corresponding ends through a via; wherein, each of the lower layer metal coils is consisted of plural layers of metal lines which are interconnected. With the same chip area, the stacked inductor of the present invention can achieve higher inductance and Q factor because of the mutual inductance generated from the plural layers of metal lines and the reduced parasitic resistance.

Abstract: A structure of stack differential inductor is represented in this invention; this structure includes top and bottom metal traces, which are aligned with each other and symmetric. Starting from one port and after half turn, the top metal trace is connected to bottom metal trace through via holes. Meanwhile, after another half turn, the bottom trace is connected to top trace through via holes. The inductance is increased by means of this method. With the same chip area, this stack differential inductor possesses larger inductance and higher Q factor because of the larger mutual inductance between top and bottom metal than conventional differential inductor.

Abstract: A multi-path stacked inductor for current compensation is represented in this invention. This structure includes top and bottom metal trace, which are aligned with each other. Each metal trace consists of multi paths. The inner path in top metal flips over to the outer path in the bottom metal, while the outer path in top metal flips over to the inner path in the bottom metal. These paths join together at the end of the metal trace with via holes. Skin effect and current crowding effect are reduced by means of this method. This stacked inductor possesses larger inductance than single layer spiral inductor, with relatively higher Q factor.